Note: Courses can be run at your site, at Morgan Advanced Programmable Systems (Orono, MN), or at a conference room near you. Please contact us at (952) 486-8881 or via this contact form.
Start | Days | Course | City | State | Register |
---|---|---|---|---|---|
03/03/2025 | 1 | Designing with the Versal Adaptive SoC Network on Chip (ACAP-NOC) | Naperville | IL | Closed |
03/03/2025 | 2 | Designing with the Versal Adaptive SoC Power and Board Design (ACAP-POWER-BD) | Naperville | IL | Closed |
03/03/2025 | 2 | Designing with the Versal Adaptive SoC Architecture (ACAP-VARCH) | Schaumburg | IL | Full |
03/03/2025 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Orono (Minneapolis) | MN | Closed |
03/03/2025 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Closed |
03/03/2025 | 2 | Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) | Orono (Minneapolis) | MN | Full |
03/03/2025 | 2 | Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) | Online | Online | Full |
03/04/2025 | 3 | Designing with VHDL (LANG-VHDL) | Online | Online | Closed |
03/04/2025 | 3 | Designing with VHDL (LANG-VHDL) | Olathe | KS | Closed |
03/05/2025 | 3 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Orono (Minneapolis) | MN | Full |
03/05/2025 | 3 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Online | Online | Full |
03/05/2025 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Orono (Minneapolis) | MN | Full |
03/05/2025 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Full |
03/06/2025 | 2 | Designing with the Versal Adaptive SoC Power and Board Design (ACAP-POWER-BD) | Champaign-Urbana | IL | Closed |
03/06/2025 | 2 | Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) | Champaign-Urbana | IL | Closed |
03/06/2025 | 2 | Design Closure Techniques (FPGA-DSGNCLOSURE) | Orono (Minneapolis) | MN | Closed |
03/06/2025 | 2 | Design Closure Techniques (FPGA-DSGNCLOSURE) | Online | Online | Closed |
03/06/2025 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Orono (Minneapolis) | MN | Full |
03/06/2025 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Online | Online | Full |
03/06/2025 | 2 | Designing with SystemVerilog (LANG-SVDES) | Olathe | KS | Closed |
03/10/2025 | 1 | Designing with the Versal Adaptive SoC Network on Chip (ACAP-NOC) | Saint Louis | MO | Closed |
03/10/2025 | 2 | Designing with the Versal Adaptive SoC PCI Express Systems (ACAP-PCIE) | Orono (Minneapolis) | MN | Closed |
03/10/2025 | 2 | Designing with the Versal Adaptive SoC PCI Express Systems (ACAP-PCIE) | Online | Online | Closed |
03/10/2025 | 2 | Designing with Versal AI Engine Architecture and Design Flow - 1 (AIE-ARCH) | Online | Online | Full |
03/10/2025 | 2 | Designing with Versal AI Engine Architecture and Design Flow - 1 (AIE-ARCH) | Fargo | ND | Full |
03/10/2025 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Naperville | IL | Closed |
03/10/2025 | 2 | High-Level Synthesis with the Vitis Unified IDE (DSP-HLS) | Orono (Minneapolis) | MN | Closed |
03/10/2025 | 2 | High-Level Synthesis with the Vitis Unified IDE (DSP-HLS) | Online | Online | Closed |
03/10/2025 | 2 | Embedded Heterogeneous Design (EMBD-HET) | Olathe | KS | Closed |
03/11/2025 | 2 | Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 (AIE-GRAPH) | Fargo | ND | Closed |
03/12/2025 | 3 | Designing with the Versal Adaptive SoC Design Methodology (ACAP-VDM) | Orono (Minneapolis) | MN | Full |
03/12/2025 | 3 | Designing with the Versal Adaptive SoC Design Methodology (ACAP-VDM) | Online | Online | Full |
03/12/2025 | 2 | Vitis Model Composer A MATLAB and Simulink-based Product (DSP-MCSIM) | Orono (Minneapolis) | MN | Closed |
03/12/2025 | 2 | Vitis Model Composer A MATLAB and Simulink-based Product (DSP-MCSIM) | Online | Online | Closed |
03/12/2025 | 2 | Adaptive SoCs for System Architects (MPSOC-ACAP-SA) | Overland Park | KS | Full |
03/13/2025 | 2 | Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) | Olathe | KS | Closed |
03/13/2025 | 2 | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite (FPGA-DFX) | Naperville | IL | Closed |
03/17/2025 | 3 | Embedded Systems Software Design (EMBD-SW) | Olathe | KS | Full |
03/18/2025 | 2 | Developing Multimedia Solutions Using a Hardened VCU-VDU (EMBD-MMEDIA) | Overland Park | KS | Closed |
03/18/2025 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Schaumburg | IL | Full |
03/18/2025 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Full |
03/18/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Orono (Minneapolis) | MN | Register |
03/18/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Online | Online | Register |
03/19/2025 | 2 | Designing an Integrated PCI Express System (CONN-PCIE) | Orono (Minneapolis) | MN | Register |
03/19/2025 | 2 | Designing an Integrated PCI Express System (CONN-PCIE) | Online | Online | Register |
03/19/2025 | 3 | Designing with Verilog (LANG-VERILOG) | Orono (Minneapolis) | MN | Register |
03/19/2025 | 3 | Designing with Verilog (LANG-VERILOG) | Online | Online | Register |
03/19/2025 | 2 | Zynq UltraScale+ MPSoC Boot and Platform Management (MPSOC-BOOT-PM) | Orono (Minneapolis) | MN | Register |
03/19/2025 | 2 | Zynq UltraScale+ MPSoC Boot and Platform Management (MPSOC-BOOT-PM) | Online | Online | Register |
03/20/2025 | 2 | Designing with Versal AI Engine Architecture and Design Flow - 1 (AIE-ARCH) | Orono (Minneapolis) | MN | Register |
03/20/2025 | 2 | Designing with Versal AI Engine Architecture and Design Flow - 1 (AIE-ARCH) | Online | Online | Register |
03/20/2025 | 2 | Developing AI Inference Solutions with the Vitis AI Platform (AI-INFER) | Chicago | IL | Register |
03/20/2025 | 2 | Zynq SoC System Architecture (EMBD-ZSA) | Chicago | IL | Register |
03/20/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Orono (Minneapolis) | MN | Register |
03/20/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Register |
03/24/2025 | 1 | Designing with the Versal Adaptive SoC Hardware Debug (ACAP-DEBUG) | Orono (Minneapolis) | MN | Register |
03/24/2025 | 1 | Designing with the Versal Adaptive SoC Hardware Debug (ACAP-DEBUG) | Online | Online | Register |
03/24/2025 | 2 | Designing with the Versal Adaptive SoC Power and Board Design (ACAP-POWER-BD) | Online | Online | Register |
03/24/2025 | 2 | Designing with the Versal Adaptive SoC Power and Board Design (ACAP-POWER-BD) | Fargo | ND | Register |
03/24/2025 | 2 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Orono (Minneapolis) | MN | Register |
03/24/2025 | 2 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Online | Online | Register |
03/24/2025 | 2 | UltraFast Design Methodology (FPGA-VDM) | Orono (Minneapolis) | MN | Register |
03/24/2025 | 2 | UltraFast Design Methodology (FPGA-VDM) | Online | Online | Register |
03/25/2025 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Orono (Minneapolis) | MN | Register |
03/25/2025 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Online | Online | Register |
03/26/2025 | 1 | Designing with the Versal Adaptive SoC Network on Chip (ACAP-NOC) | Saint Louis | MO | #REF! |
03/26/2025 | 3 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Orono (Minneapolis) | MN | Register |
03/26/2025 | 3 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Online | Online | Register |
03/26/2025 | 3 | Designing with the Zynq UltraScale+ RFSoC (AI-ACCEL) | Orono (Minneapolis) | MN | Register |
03/26/2025 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Register |
03/26/2025 | 2 | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite (FPGA-DFX) | Orono (Minneapolis) | MN | Register |
03/26/2025 | 2 | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite (FPGA-DFX) | Online | Online | Register |
03/26/2025 | 3 | Designing with VHDL (LANG-VHDL) | Orono (Minneapolis) | MN | Register |
03/26/2025 | 3 | Designing with VHDL (LANG-VHDL) | Online | Online | Register |
03/26/2025 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS (SOM-ROBOTICS) | Orono (Minneapolis) | MN | Register |
03/26/2025 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS (SOM-ROBOTICS) | Online | Online | Register |
03/27/2025 | 2 | Designing with the Versal Adaptive SoC Memory Interfaces (ACAP-MEM) | Overland Park | KS | Register |
03/27/2025 | 2 | Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 (AIE-GRAPH) | Fargo | ND | Register |
03/27/2025 | 2 | Design Closure Techniques (FPGA-DSGNCLOSURE) | Orono (Minneapolis) | MN | Register |
03/27/2025 | 2 | Design Closure Techniques (FPGA-DSGNCLOSURE) | Online | Online | Register |
03/27/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Orono (Minneapolis) | MN | Register |
03/27/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Register |
03/28/2025 | 1 | Designing with Versal AI Engine DSP Applications (AIE-DSP) | Cedar Rapids | IA | Register |
03/28/2025 | 1 | Migrating to the Vitis Unified IDE (EMBD-VITIS) | Cedar Rapids | IA | Register |
03/31/2025 | 1 | Migrating from UltraScale+ Devices to Versal Adaptive SoCs (ACAP-MGRT) | Orono (Minneapolis) | MN | Register |
03/31/2025 | 1 | Migrating from UltraScale+ Devices to Versal Adaptive SoCs (ACAP-MGRT) | Online | Online | Register |
03/31/2025 | 1 | Designing with the Versal Adaptive SoC Network on Chip (ACAP-NOC) | Naperville | IL | Register |
03/31/2025 | 2 | Embedded Systems Design (EMBD-HW) | Online | Online | Register |
03/31/2025 | 2 | Embedded Systems Design (EMBD-HW) | Fargo | ND | Register |
03/31/2025 | 2 | Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) | Chicago | IL | Register |
03/31/2025 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Orono (Minneapolis) | MN | Register |
03/31/2025 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Online | Online | Register |
03/31/2025 | 2 | Advanced VHDL (LANG-ADVVHDL) | Orono (Minneapolis) | MN | Register |
03/31/2025 | 2 | Advanced VHDL (LANG-ADVVHDL) | Online | Online | Register |
04/01/2025 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Orono (Minneapolis) | MN | Register |
04/01/2025 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Register |
04/02/2025 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Orono (Minneapolis) | MN | Register |
04/02/2025 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Register |
04/03/2025 | 2 | Designing with Versal AI Engine Architecture and Design Flow - 1 (AIE-ARCH) | Orono (Minneapolis) | MN | Register |
04/03/2025 | 2 | Designing with Versal AI Engine Architecture and Design Flow - 1 (AIE-ARCH) | Online | Online | Register |
04/03/2025 | 2 | Designing with Versal AI Engine Kernel Programming and Optimization - 3 (AIE-KERNEL) | Olathe | KS | Register |
04/03/2025 | 2 | Developing Multimedia Solutions Using a Hardened VCU-VDU (EMBD-MMEDIA) | Orono (Minneapolis) | MN | Register |
04/03/2025 | 2 | Developing Multimedia Solutions Using a Hardened VCU-VDU (EMBD-MMEDIA) | Online | Online | Register |
04/03/2025 | 2 | Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) | Hoffman Estates | IL | Register |
04/03/2025 | 2 | Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) | Schaumburg | IL | Register |
04/03/2025 | 2 | Adaptive SoCs for System Architects (MPSOC-ACAP-SA) | Saint Louis | MO | Register |
04/07/2025 | 1 | Designing with the Versal Adaptive SoC Hardware Debug (ACAP-DEBUG) | Saint Louis | MO | Register |
04/07/2025 | 1 | Designing with the Versal Adaptive SoC Quick Start (ACAP-QSTART) | Orono (Minneapolis) | MN | Register |
04/07/2025 | 1 | Designing with the Versal Adaptive SoC Quick Start (ACAP-QSTART) | Online | Online | Register |
04/07/2025 | 3 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Orono (Minneapolis) | MN | Register |
04/07/2025 | 3 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Online | Online | Register |
04/07/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Schaumburg | IL | Register |
04/07/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Register |
04/07/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Orono (Minneapolis) | MN | Register |
04/07/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Online | Online | Register |
04/07/2025 | 2 | Designing with SystemVerilog (LANG-SVDES) | Overland Park | KS | Register |
04/08/2025 | 1 | Designing with the Versal Adaptive SoC Network on Chip (ACAP-NOC) | Orono (Minneapolis) | MN | Register |
04/08/2025 | 1 | Designing with the Versal Adaptive SoC Network on Chip (ACAP-NOC) | Online | Online | Register |
04/08/2025 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Orono (Minneapolis) | MN | Register |
04/08/2025 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Online | Online | Register |
04/08/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Orono (Minneapolis) | MN | Register |
04/08/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Online | Online | Register |
04/08/2025 | 2 | Using Vision-based Applications with the Kria KV260 Vision AI (SOM-VISION) | Champaign-Urbana | IL | Register |
04/09/2025 | 3 | Designing with the Versal Adaptive SoC Design Methodology (ACAP-VDM) | Orono (Minneapolis) | MN | Register |
04/09/2025 | 3 | Designing with the Versal Adaptive SoC Design Methodology (ACAP-VDM) | Online | Online | Register |
04/09/2025 | 1 | Migrating to the Vitis Unified IDE (EMBD-VITIS) | Champaign-Urbana | IL | Register |
04/10/2025 | 2 | Designing with the Versal Adaptive SoC PCI Express Systems (ACAP-PCIE) | Champaign-Urbana | IL | Register |
04/10/2025 | 2 | Designing with the Versal Adaptive SoC Architecture (ACAP-VARCH) | Orono (Minneapolis) | MN | Register |
04/10/2025 | 2 | Designing with the Versal Adaptive SoC Architecture (ACAP-VARCH) | Online | Online | Register |
04/10/2025 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Orono (Minneapolis) | MN | Register |
04/10/2025 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Online | Online | Register |
04/10/2025 | 2 | Zynq UltraScale+ MPSoC Boot and Platform Management (MPSOC-BOOT-PM) | Orono (Minneapolis) | MN | Register |
04/10/2025 | 2 | Zynq UltraScale+ MPSoC Boot and Platform Management (MPSOC-BOOT-PM) | Online | Online | Register |
04/11/2025 | 1 | Designing with Versal AI Engine DSP Applications (AIE-DSP) | Naperville | IL | Register |
04/14/2025 | 1 | Designing with the Versal Adaptive SoC Serial Transceivers (ACAP-TRX) | Saint Louis | MO | Register |
04/14/2025 | 2 | Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 (AIE-GRAPH) | Champaign-Urbana | IL | Register |
04/14/2025 | 2 | Design Closure Techniques (FPGA-DSGNCLOSURE) | Orono (Minneapolis) | MN | Register |
04/14/2025 | 2 | Design Closure Techniques (FPGA-DSGNCLOSURE) | Online | Online | Register |
04/14/2025 | 3 | Designing with Verilog (LANG-VERILOG) | Overland Park | KS | Register |
04/14/2025 | 3 | Operating Systems and Hypervisors in Adaptive SoCs (SOC-OS-HYPER) | Overland Park | KS | Register |
04/16/2025 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS (SOM-ROBOTICS) | Orono (Minneapolis) | MN | Register |
04/16/2025 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS (SOM-ROBOTICS) | Online | Online | Register |
04/17/2025 | 2 | Designing with the Versal Adaptive SoC Power and Board Design (ACAP-POWER-BD) | Orono (Minneapolis) | MN | Register |
04/17/2025 | 2 | Designing with the Versal Adaptive SoC Power and Board Design (ACAP-POWER-BD) | Online | Online | Register |
04/17/2025 | 2 | Designing with Versal AI Engine Kernel Programming and Optimization - 3 (AIE-KERNEL) | Orono (Minneapolis) | MN | Register |
04/17/2025 | 2 | Designing with Versal AI Engine Kernel Programming and Optimization - 3 (AIE-KERNEL) | Online | Online | Register |
04/17/2025 | 2 | Developing AI Inference Solutions with the Vitis AI Platform (AI-INFER) | Orono (Minneapolis) | MN | Register |
04/17/2025 | 2 | Developing AI Inference Solutions with the Vitis AI Platform (AI-INFER) | Online | Online | Register |
04/17/2025 | 2 | Embedded Heterogeneous Design (EMBD-HET) | Fargo | ND | Register |
04/18/2025 | 1 | Designing with the Versal Adaptive SoC Network on Chip (ACAP-NOC) | Schaumburg | IL | Register |
04/21/2025 | 1 | Designing with Versal AI Engine DSP Applications (AIE-DSP) | Olathe | KS | Register |
04/21/2025 | 2 | Embedded Systems Design (EMBD-HW) | Olathe | KS | Register |
04/21/2025 | 3 | Embedded Systems Software Design (EMBD-SW) | Olathe | KS | Register |
04/21/2025 | 1 | Migrating to the Vitis Unified IDE (EMBD-VITIS) | Orono (Minneapolis) | MN | Register |
04/21/2025 | 1 | Migrating to the Vitis Unified IDE (EMBD-VITIS) | Online | Online | Register |
04/21/2025 | 2 | Zynq SoC System Architecture (EMBD-ZSA) | Orono (Minneapolis) | MN | Register |
04/21/2025 | 2 | Zynq SoC System Architecture (EMBD-ZSA) | Online | Online | Register |
04/21/2025 | 2 | Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) | Orono (Minneapolis) | MN | Register |
04/21/2025 | 2 | Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) | Online | Online | Register |
04/21/2025 | 2 | UltraFast Design Methodology (FPGA-VDM) | Orono (Minneapolis) | MN | Register |
04/21/2025 | 2 | UltraFast Design Methodology (FPGA-VDM) | Online | Online | Register |
04/21/2025 | 3 | Designing with VHDL (LANG-VHDL) | Schaumburg | IL | Register |
04/23/2025 | 2 | Designing an Integrated PCI Express System (CONN-PCIE) | Orono (Minneapolis) | MN | Register |
04/23/2025 | 2 | Designing an Integrated PCI Express System (CONN-PCIE) | Online | Online | Register |
04/23/2025 | 2 | Vitis Model Composer A MATLAB and Simulink-based Product (DSP-MCSIM) | Naperville | IL | Register |
04/24/2025 | 2 | Designing with the Versal Adaptive SoC Memory Interfaces (ACAP-MEM) | Saint Louis | MO | Register |
04/25/2025 | 1 | Designing with the Versal Adaptive SoC Hardware Debug (ACAP-DEBUG) | Overland Park | KS | Register |
04/25/2025 | 1 | Migrating from UltraScale+ Devices to Versal Adaptive SoCs (ACAP-MGRT) | Overland Park | KS | Register |
04/28/2025 | 1 | Designing with the Versal Adaptive SoC Network on Chip (ACAP-NOC) | Champaign-Urbana | IL | Register |
04/28/2025 | 1 | Designing with Versal AI Engine Quick Start (AIE-QSTART) | Orono (Minneapolis) | MN | Register |
04/28/2025 | 1 | Designing with Versal AI Engine Quick Start (AIE-QSTART) | Online | Online | Register |
04/28/2025 | 2 | High-Level Synthesis with the Vitis Unified IDE (DSP-HLS) | Orono (Minneapolis) | MN | Register |
04/28/2025 | 2 | High-Level Synthesis with the Vitis Unified IDE (DSP-HLS) | Online | Online | Register |
04/28/2025 | 2 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Fargo | ND | Register |
04/28/2025 | 2 | Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) | Orono (Minneapolis) | MN | Register |
04/28/2025 | 2 | Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) | Online | Online | Register |
04/28/2025 | 2 | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite (FPGA-DFX) | Orono (Minneapolis) | MN | Register |
04/28/2025 | 2 | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite (FPGA-DFX) | Online | Online | Register |
04/28/2025 | 2 | Verification with SystemVerilog (LANG-SVVER) | Olathe | KS | Register |
04/29/2025 | 1 | Designing with the Versal Adaptive SoC Serial Transceivers (ACAP-TRX) | Chicago | IL | Register |
04/29/2025 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Orono (Minneapolis) | MN | Register |
04/29/2025 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Online | Online | Register |
04/30/2025 | 1 | Designing with the Versal Adaptive SoC Quick Start (ACAP-QSTART) | Orono (Minneapolis) | MN | Register |
04/30/2025 | 1 | Designing with the Versal Adaptive SoC Quick Start (ACAP-QSTART) | Online | Online | Register |
04/30/2025 | 3 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Orono (Minneapolis) | MN | Register |
04/30/2025 | 3 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Online | Online | Register |
04/30/2025 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Orono (Minneapolis) | MN | Register |
04/30/2025 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Register |
04/30/2025 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Orono (Minneapolis) | MN | Register |
04/30/2025 | 3 | Vivado STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Register |
05/01/2025 | 2 | Designing with Versal AI Engine Architecture and Design Flow - 1 (AIE-ARCH) | Schaumburg | IL | Register |
05/01/2025 | 2 | Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) | Schaumburg | IL | Register |
05/01/2025 | 2 | Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) | Schaumburg | IL | Register |
05/01/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Orono (Minneapolis) | MN | Register |
05/01/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Online | Online | Register |
05/01/2025 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS (SOM-ROBOTICS) | Orono (Minneapolis) | MN | Register |
05/01/2025 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS (SOM-ROBOTICS) | Online | Online | Register |
05/02/2025 | 1 | Designing with Versal AI Engine DSP Applications (AIE-DSP) | Orono (Minneapolis) | MN | Register |
05/02/2025 | 1 | Designing with Versal AI Engine DSP Applications (AIE-DSP) | Online | Online | Register |
05/02/2025 | 1 | Migrating to the Vitis Unified IDE (EMBD-VITIS) | Orono (Minneapolis) | MN | Register |
05/02/2025 | 1 | Migrating to the Vitis Unified IDE (EMBD-VITIS) | Online | Online | Register |
05/05/2025 | 2 | Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 (AIE-GRAPH) | Orono (Minneapolis) | MN | Register |
05/05/2025 | 2 | Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2 (AIE-GRAPH) | Online | Online | Register |
05/05/2025 | 2 | Design Closure Techniques (FPGA-DSGNCLOSURE) | Orono (Minneapolis) | MN | Register |
05/05/2025 | 2 | Design Closure Techniques (FPGA-DSGNCLOSURE) | Online | Online | Register |
05/05/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Orono (Minneapolis) | MN | Register |
05/05/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Register |
05/07/2025 | 1 | Designing with Versal AI Engine Quick Start (AIE-QSTART) | Olathe | KS | Register |
05/08/2025 | 2 | Designing with Versal AI Engine Kernel Programming and Optimization - 3 (AIE-KERNEL) | Cedar Rapids | IA | Register |
05/08/2025 | 2 | Developing Multimedia Solutions Using a Hardened VCU-VDU (EMBD-MMEDIA) | Cedar Rapids | IA | Register |
05/08/2025 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Orono (Minneapolis) | MN | Register |
05/08/2025 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Online | Online | Register |
05/08/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Chicago | IL | Register |
05/12/2025 | 1 | Designing with the Versal Adaptive SoC Serial Transceivers (ACAP-TRX) | Chicago | IL | Register |
05/12/2025 | 3 | Operating Systems and Hypervisors in Adaptive SoCs (SOC-OS-HYPER) | Chicago | IL | Register |
05/12/2025 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS (SOM-ROBOTICS) | Online | Online | Register |
05/12/2025 | 1 | Using Robotics Applications with the Kria KR260 Robotics Starter Kit and KRS (SOM-ROBOTICS) | Naperville | IL | Register |
05/14/2025 | 3 | Designing with Verilog (LANG-VERILOG) | Overland Park | KS | Register |
05/19/2025 | 1 | Designing with the Versal Adaptive SoC Quick Start (ACAP-QSTART) | Fargo | ND | Register |
05/19/2025 | 2 | Vitis Model Composer A MATLAB and Simulink-based Product (DSP-MCSIM) | Orono (Minneapolis) | MN | Register |
05/19/2025 | 2 | Vitis Model Composer A MATLAB and Simulink-based Product (DSP-MCSIM) | Online | Online | Register |
05/19/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Orono (Minneapolis) | MN | Register |
05/19/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Online | Online | Register |
05/19/2025 | 2 | Zynq UltraScale+ MPSoC Boot and Platform Management (MPSOC-BOOT-PM) | Orono (Minneapolis) | MN | Register |
05/19/2025 | 2 | Zynq UltraScale+ MPSoC Boot and Platform Management (MPSOC-BOOT-PM) | Online | Online | Register |
05/21/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Orono (Minneapolis) | MN | Register |
05/21/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Register |
05/21/2025 | 3 | Designing with VHDL (LANG-VHDL) | Orono (Minneapolis) | MN | Register |
05/21/2025 | 3 | Designing with VHDL (LANG-VHDL) | Online | Online | Register |
05/22/2025 | 2 | Embedded Heterogeneous Design (EMBD-HET) | Schaumburg | IL | Register |
05/27/2025 | 1 | Designing with the Versal Adaptive SoC Serial Transceivers (ACAP-TRX) | Orono (Minneapolis) | MN | Register |
05/27/2025 | 1 | Designing with the Versal Adaptive SoC Serial Transceivers (ACAP-TRX) | Online | Online | Register |
05/27/2025 | 2 | Adaptive SoCs for System Architects (MPSOC-ACAP-SA) | Orono (Minneapolis) | MN | Register |
05/27/2025 | 2 | Adaptive SoCs for System Architects (MPSOC-ACAP-SA) | Online | Online | Register |
05/27/2025 | 2 | Using Vision-based Applications with the Kria KV260 Vision AI (SOM-VISION) | Schaumburg | IL | Register |
05/29/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Orono (Minneapolis) | MN | Register |
05/29/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Online | Online | Register |
05/30/2025 | 1 | Designing with Versal AI Engine Quick Start (AIE-QSTART) | Orono (Minneapolis) | MN | Register |
05/30/2025 | 1 | Designing with Versal AI Engine Quick Start (AIE-QSTART) | Online | Online | Register |
Don't see a class?
If you do not see a class that you're interested in on the schedule, please either give us a call or contact us. We will work to rearrange the schedule so that key members of your team can get the Xilinx training they need as soon as possible.
Cancellation Policies
These are our cancellation policies:
Student Cancellation Policy
- Students cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
- Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
- Student cancellations must be sent here.
Course Cancellation Policy
- We regret that from time to time classes will need to be rescheduled or cancelled.
- In the event of cancellation, live on-line training may be offered as a substitute.
- Morgan Advanced Programmable Systems, Inc. may cancel a class up to 7 days before the scheduled start date of the class; all students will be entitled to a 100% refund.
- Under no circumstances is Morgan Advanced Programmable Systems, Inc. responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.
- For additional information or to schedule a private class contact us here.