As FPGAs and ACAP devices break the 50 billion transistor threshold, traditional design techniques the HDLs and baremetal operating systems are not scaling in a way that allows a reasonable time to market with a reasonably sized design team.  Engineers today are expected to do more in less time and more reliably.  Fortunately, Xilinx understands this situation and has invested in new design entry methodologies that will scale to state of the art FPGAs.