Course Schedule (updated frequently)
Date Course City State Register Description
October 2018
Oct 1-2 Designing FPGAs using the Vivado Design Suite 2 (FPGA-VDES2) St. Louis MO Closed Description
Oct 2-3 Embedded Design with PetaLinux Tools (EMBD-PLNX) Madison WI Full Description
Oct 4-5 Designing FPGAs using the Vivado Design Suite 1 (FPGA-VDES1) Madison WI Closed Description
Oct 4-5 Designing FPGAs using the Vivado Design Suite 3 (FPGA-VDES3) St. Louis MO Full Description
Oct 8-9 Designing FPGAs using the Vivado Design Suite 4 (FPGA-VDES4) St. Louis MO Full Description
Oct 8-9 Designing FPGAs using the Vivado Design Suite 2 (FPGA-VDES2) Orono (Minneapolis) MN Register Description
Oct 11-12 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Schaumburg IL Register Description
Oct 15-16 Zynq SoC System Architecture (EMBD-ZSA) Orono (Minneapolis) MN Register Description
Oct 15-17 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Overland Park KS Register Description
Oct 17-18 Embedded Systems Software Design (EMBD-SW) Bloomington (Minneapolis) MN Register Description
Oct 18-19 Embedded Systems Design (EMBD-HW) Orono (Minneapolis) MN Register Description
Oct 22-24 Designing with VHDL (LANG-VHDL) Orono MN Register Description
Oct 22-23 Designing with the 7 Series Families (FPGA-7SERIES) Wichita KS Register Description
Oct 23-24 Embedded Design with PetaLinux Tools (EMBD-PLNX) Cedar Rapids IA Register Description
Oct 24-25 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Wichita KS Register Description
Oct 29-30 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) Schaumburg IL Register Description
November 2018
Nov 1-2 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Schaumburg IL Register Description
Nov 5 SDSoC Development Environment and Methodology (EMBD-SDSOC) Orono (Minneapolis) MN Register Description
Nov 5-6 Designing FPGAs using the Vivado Design Suite 1 (FPGA-VDES1) Milwaukee WI Register Description
Nov 6-7 Advanced SDSoC Development Environment and Methodology (EMBD-ADVSDSOC) Orono (Minneapolis) MN Register Description
Nov 8-9 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Bloomington MN Register Description
Nov 8-9 Advanced VHDL (LANG-ADVVHDL) Orono (Minneapolis) MN Register Description
Nov 12-13 Embedded Systems Design (EMBD-HW) Overland Park KS Register Description
Nov 12-13 Designing FPGAs using the Vivado Design Suite 2 (FPGA-VDES2) Milwaukee WI Register Description
Nov 12-13 Embedded Systems Design (EMBD-HW) Overland Park KS Register Description
Nov 12-14 Designing with VHDL (LANG-VHDL) Olathe KS Register Description
Nov 14-15 Embedded Systems Software Design (EMBD-SW) Overland Park KS Register Description
Nov 15-16 Advanced VHDL (LANG-ADVVHDL) Olathe KS Register Description
Nov 26-27 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Nov 28-29 Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) Orono (Minneapolis) MN Register Description
Nov 29-30 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) Schaumburg IL Register Description
December 2018
Dec 3-4 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) Orono (Minneapolis) MN Register Description
Dec 5-6 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Dec 5-6 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) St. Louis MO Register Description
Dec 10-11 Designing FPGAs using the Vivado Design Suite 3 (FPGA-VDES3) Orono (Minneapolis) MN Register Description
Dec 12-14 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Orono (Minneapolis) MN Register Description
Dec 17-18 Designing FPGAs using the Vivado Design Suite 1 (FPGA-VDES1) Madison WI Register Description
Dec 17-18 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Cedar Rapids IA Register Description
Dec 19-21 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Madison WI Register Description
January 2019
Jan 7-9 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) CedarRapids IA Register Description
Jan 10-11 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) CedarRapids IA Register Description
Jan 21-22 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description

Student Cancellation Policy

  • Students cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
  • Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
  • Student cancellations must be sent here.

Course Cancellation Policy

  • We regret from time to time classes will need to be rescheduled or cancelled.
  • In the event of cancellation, live on-line training may be offered as a substitute.
  • Morgan Advanced Programmable Systems, Inc. may cancel a class up to 7 days before the scheduled start date of the class; all students will be entitled to a 100% refund.
  • Under no circumstances is Morgan Advanced Programmable Systems, Inc. responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.
  • For additional information or to schedule a private class contact us here.