| April | 2020 | ||||
| Date | Course | City | State | Register | Description |
| Apr 2-3 | C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) | Orono (Minneapolis) | MN | Register | Description |
| Apr 2-3 | C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) | Online | Online | Register | Description |
| Apr 6-7 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Orono (Minneapolis) | MN | Register | Description |
| Apr 6-7 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Online | Online | Register | Description |
| Apr 8-8 | Vitis Introduction Workshop (VITIS-1D) | Orono (Minneapolis) | MN | Register | Description |
| Apr 8-8 | Vitis Introduction Workshop (VITIS-1D) | Online | Online | Register | Description |
| Apr 9-10 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Orono (Minneapolis) | MN | Register | Description |
| Apr 9-10 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Register | Description |
| Apr 13-15 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Register | Description |
| Apr 13-14 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Orono (Minneapolis) | MN | Register | Description |
| Apr 13-14 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Online | Online | Register | Description |
| Apr 14-14 | Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) | Orono (Minneapolis) | MN | Register | Description |
| Apr 14-14 | Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) | Online | Online | Register | Description |
| Apr 16-16 | Vitis Introduction Workshop (VITIS-1D) | Online | Online | Register | Description |
| Apr 17-17 | Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) | Orono (Minneapolis) | MN | Register | Description |
| Apr 17-17 | Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) | Online | Online | Register | Description |
| Apr 20-21 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Orono (Minneapolis) | MN | Register | Description |
| Apr 20-21 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Online | Online | Register | Description |
| Apr 20-21 | C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) | Schaumburg | IL | Register | Description |
| Apr 20-21 | C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) | Orono (Minneapolis) | MN | Register | Description |
| Apr 20-24 | Zynq MPSoC Master Training for Experienced FPGA Engineers (EMBD-33040) | Orono (Minneapolis) | MN | Register | Description |
| Apr 20-22 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Schaumburg | IL | Register | Description |
| Apr 20-22 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Orono (Minneapolis) | MN | Register | Description |
| Apr 20-22 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Register | Description |
| Apr 21-23 | Designing with VHDL (LANG-VHDL) | Online | Online | Register | Description |
| Apr 21-23 | Designing with VHDL (LANG-VHDL) | Bloomington | MN | Register | Description |
| Apr 22-24 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Orono (Minneapolis) | MN | Register | Description |
| Apr 22-24 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Register | Description |
| Apr 27-28 | Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) | Orono (Minneapolis) | MN | Register | Description |
| Apr 29-May 1 | Designing with Verilog (LANG-VERILOG) | Orono (Minneapolis) | MN | Register | Description |
| Apr 29-May 1 | Designing with Verilog (LANG-VERILOG) | Online | Online | Register | Description |
| Apr 30-May 1 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Schaumburg | IL | Register | Description |
| Apr 30-May 1 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Orono (Minneapolis) | MN | Register | Description |
| Apr 30-May 1 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Online | Online | Register | Description |
| May | 2020 | ||||
| Date | Course | City | State | Register | Description |
| May 4-5 | C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) | Orono (Minneapolis) | MN | Register | Description |
| May 4-5 | C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) | Online | Online | Register | Description |
| May 4-5 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Schaumburg | IL | Register | Description |
| May 6-7 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Naperville | IL | Register | Description |
| May 7-8 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Orono (Minneapolis) | MN | Register | Description |
| May 11-12 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Schaumburg | IL | Register | Description |
| May 11-13 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Orono (Minneapolis) | MN | Register | Description |
| May 11-13 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Register | Description |
| May 11-12 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Naperville | IL | Register | Description |
| May 11-13 | Designing with Verilog (LANG-VERILOG) | Orono (Minneapolis) | MN | Register | Description |
| May 11-13 | Designing with Verilog (LANG-VERILOG) | Online | Online | Register | Description |
| May 14-15 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Naperville | IL | Register | Description |
| May 14-15 | Designing with SystemVerilog (LANG-SVDES) | Orono (Minneapolis) | MN | Register | Description |
| May 14-15 | Designing with SystemVerilog (LANG-SVDES) | Online | Online | Register | Description |
| May 18-19 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Overland Park | KS | Register | Description |
| May 18-22 | Zynq MPSoC Master Training for Experienced FPGA Engineers (EMBD-33040) | Orono (Minneapolis) | MN | Register | Description |
| May 18-20 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Orono (Minneapolis) | MN | Register | Description |
| May 18-20 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Register | Description |
| May 19-20 | Embedded Systems Software Design (EMBD-SW) | Overland Park | KS | Register | Description |
| May 20-22 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Saint Louis | MO | Register | Description |
| May 20-21 | Embedded Systems Software Design (EMBD-SW) | Orono (Minneapolis) | MN | Register | Description |
| May 20-21 | Embedded Systems Software Design (EMBD-SW) | Online | Online | Register | Description |
| May 21-22 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Fargo | ND | Register | Description |
| May 21-22 | Embedded Systems Software Design (EMBD-SW) | Orono (Minneapolis) | MN | Register | Description |
| May 22-22 | Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) | Saint Louis | MO | Register | Description |
| May 25-27 | Designing with Verilog (LANG-VERILOG) | Rockford | IL | Register | Description |
| May 25-27 | Designing with VHDL (LANG-VHDL) | Schaumburg | IL | Register | Description |
| May 28-29 | Advanced VHDL (LANG-ADVVHDL) | Schaumburg | IL | Register | Description |
| May 28-29 | Designing with SystemVerilog (LANG-SVDES) | Rockford | IL | Register | Description |
| June | 2020 | ||||
| Date | Course | City | State | Register | Description |
| Jun 1-2 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Schaumburg | IL | Register | Description |
| Jun 1-2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Saint Louis | MO | Register | Description |
| Jun 3-5 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Schaumburg | IL | Register | Description |
| Jun 4-5 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Saint Louis | MO | Register | Description |
| Jun 8-9 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Orono (Minneapolis) | MN | Register | Description |
| Jun 8-9 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Saint Louis | MO | Register | Description |
| Jun 8-10 | Designing with Verilog (LANG-VERILOG) | Orono (Minneapolis) | MN | Register | Description |
| Jun 8-10 | Designing with Verilog (LANG-VERILOG) | Online | Online | Register | Description |
| Jun 9-10 | Embedded Systems Software Design (EMBD-SW) | Orono (Minneapolis) | MN | Register | Description |
| Jun 10-11 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Orono (Minneapolis) | MN | Register | Description |
| Jun 11-12 | C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) | Online | Online | Register | Description |
| Jun 11-12 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Saint Louis | MO | Register | Description |
| Jun 12-12 | Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) | Orono (Minneapolis) | MN | Register | Description |
| Jun 15-16 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Schaumburg | IL | Register | Description |
| Jun 16-17 | Embedded Systems Software Design (EMBD-SW) | Schaumburg | IL | Register | Description |
| Jun 17-18 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Schaumburg | IL | Register | Description |
| Jun 19-19 | Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) | Schaumburg | IL | Register | Description |
| Jun 22-24 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Schaumburg | IL | Register | Description |
| Jun 22-23 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Saint Louis | MO | Register | Description |
| Jun 24-26 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Cedar Rapids | IA | Register | Description |
| Jun 24-25 | Embedded Systems Software Design (EMBD-SW) | Saint Louis | MO | Register | Description |
| Jun 29-Jul 1 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Orono (Minneapolis) | MN | Register | Description |
| Jun 29-29 | Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) | Saint Louis | MO | Register | Description |
| July | 2020 | ||||
| Date | Course | City | State | Register | Description |
| Jul 6-8 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Schaumburg | IL | Register | Description |
| Jul 9-10 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Schaumburg | IL | Register | Description |
| Jul 9-10 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Saint Louis | MO | Register | Description |
| Jul 13-14 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Saint Louis | MO | Register | Description |
| Jul 14-15 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Schaumburg | IL | Register | Description |
| Jul 15-17 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Saint Louis | MO | Register | Description |
| Jul 15-17 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Saint Louis | MO | Register | Description |
| Jul 16-17 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Schaumburg | IL | Register | Description |
| Jul 20-21 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Schaumburg | IL | Register | Description |
| Jul 22-23 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Schaumburg | IL | Register | Description |
| August | 2020 | ||||
| Date | Course | City | State | Register | Description |
| Aug 3-5 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Orono (Minneapolis) | MN | Register | Description |
| Aug 3-5 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Register | Description |
| Aug 6-7 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Orono (Minneapolis) | MN | Register | Description |
| Aug 10-11 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Schaumburg | IL | Register | Description |
| Aug 10-11 | C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) | Schaumburg | IL | Register | Description |
| Aug 10-11 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Orono (Minneapolis) | MN | Register | Description |
| Aug 10-12 | Designing with VHDL (LANG-VHDL) | Orono (Minneapolis) | MN | Register | Description |
| Aug 12-14 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Schaumburg | IL | Register | Description |
| Aug 13-13 | Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) | Schaumburg | IL | Register | Description |
| Aug 13-14 | Advanced VHDL (LANG-ADVVHDL) | Orono (Minneapolis) | MN | Register | Description |
| September | 2020 | ||||
| Date | Course | City | State | Register | Description |
| Sep 2-2 | Vitis Introduction Workshop (VITIS-1D) | Schaumburg | IL | Register | Description |
| Sep 3-3 | Advanced Features and Techniques of Embedded Systems Software Design (EMBD-ADVSW) | Schaumburg | IL | Register | Description |
| Sep 14-16 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Orono (Minneapolis) | MN | Register | Description |
| Sep 14-16 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Register | Description |
Don't see a class?
If you do not see a class that you're interested in on the schedule, please either give us a call or contact us. We will work to rearrange the schedule so that key members of your team can get the Xilinx training they need as soon as possible.
Cancellation policy
These are our cancellation policies.
Student Cancellation Policy
- Students cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
- Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
- Student cancellations must be sent here.
Course Cancellation Policy
- We regret that from time to time classes will need to be rescheduled or cancelled.
- In the event of cancellation, live on-line training may be offered as a substitute.
- Morgan Advanced Programmable Systems, Inc. may cancel a class up to 7 days before the scheduled start date of the class; all students will be entitled to a 100% refund.
- Under no circumstances is Morgan Advanced Programmable Systems, Inc. responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.
- For additional information or to schedule a private class contact us here.