August 2019
Aug 19-20 Embedded Design with PetaLinux Tools (EMBD-PLNX) Schaumburg IL Full Description
Aug 19-21 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Fargo ND Closed Description
Aug 19-20 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Brookings SD Closed Description
Aug 22-23 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Full Description
Aug 22-23 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Lincoln NE Full Description
Aug 22-23 Designing an Integrated PCI Express System (CONN-PCIE) Madison WI Closed Description
Aug 26-27 How to Design a High-Speed Memory Interface (Legacy Vivado 2015_1) (CONN-MIF) Orono (Minneapolis) MN Register Description
Aug 26-27 Designing with the 7 Series Families (FPGA-7SERIES) Cedar Rapids IA Closed Description
Aug 26-28 Designing with VHDL (LANG-VHDL) Omaha NE Closed Description
Aug 29-30 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs (EMBD-OCLSDA) Orono (Minneapolis) MN Register Description
Aug 29-30 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) Lemont IL Register Description
Aug 29-30 Vivado Design Suite for ISE PN Users (FPGA-V4ISE) Brookings SD Register Description
September 2019
Sep 2-3 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Wichita KS Closed Description
Sep 2-3 Vivado Design Suite for ISE PN Users (FPGA-V4ISE) Madison WI Closed Description
Sep 3-5 Designing with VHDL (LANG-VHDL) Orono (Minneapolis) MN Register Description
Sep 3-4 Vivado Design Suite Advanced XDC and STA for ISE Users (FPGA-VAXDC4ISE) Madison WI Register Description
Sep 3-5 Designing with Verilog (LANG-VERILOG) Omaha NE Register Description
Sep 4-6 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Cedar Rapids IA Register Description
Sep 4-5 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Orono (Minneapolis) MN Register Description
Sep 4-5 Designing with the 7 Series Families (FPGA-7SERIES) Brookings SD Register Description
Sep 4-5 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Fargo ND Register Description
Sep 5-6 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Madison WI Register Description
Sep 9-10 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Schaumburg IL Register Description
Sep 9-10 Designing an Integrated PCI Express System (CONN-PCIE) Skakopee MN Register Description
Sep 9-10 DSP Design Using System Generator (DSP-SYSGEN) Moorhead MN Register Description
Sep 11-12 DSP Design Using System Generator (DSP-SYSGEN) Schaumburg IL Register Description
Sep 11-11 Essential Tcl Scripting for the Vivado Design Suite (LANG-TCL) Overland Park KS Register Description
Sep 11-12 Embedded Design with PetaLinux Tools (EMBD-PLNX) Cedar Rapids IA Register Description
Sep 16-17 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
Sep 16-18 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Milwaukee WI Register Description
Sep 16-17 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Online Online Register Description
Sep 19-20 Advanced VHDL (LANG-ADVVHDL) Orono (Minneapolis) MN Register Description
Sep 19-19 Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) Springfield IL Register Description
Sep 19-20 Vivado Design Suite Advanced XDC and STA for ISE Users (FPGA-VAXDC4ISE) Brookings SD Register Description
Sep 23-24 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Schaumburg IL Register Description
Sep 23-23 How to Design a Xilinx Digital Signal Processing System in 1 Day (Legacy ISE 13.1) (DSP-13000) Saint Louis MO Register Description
Sep 23-24 How to Design a High-Speed Memory Interface (Legacy Vivado 2015_1) (CONN-MIF) Bloomington MN Register Description
Sep 25-26 Verification with SystemVerilog (LANG-SVVER) Lincoln NE Register Description
Sep 25-26 Designing with SystemVerilog (LANG-SVDES) Moorhead MN Register Description
Sep 25-26 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Sep 26-26 Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) Overland Park KS Register Description
October 2019
Oct 7-8 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Oct 7-8 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Brookings SD Register Description
Oct 7-8 Xilinx Partial Reconfiguration Tools and Techniques (FPGA-PR) Overland Park KS Register Description
Oct 10-11 Advanced VHDL (LANG-ADVVHDL) Orono (Minneapolis) MN Register Description
Oct 10-11 Verification with SystemVerilog (LANG-SVVER) Fargo ND Register Description
Oct 10-11 How to Design a High-Speed Memory Interface (Legacy Vivado 2015_1) (CONN-MIF) Springfield IL Register Description
Oct 14-15 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs (EMBD-OCLSDA) Schaumburg IL Register Description
Oct 14-16 Designing with VHDL (LANG-VHDL) Cedar Rapids IA Register Description
Oct 14-15 Embedded Systems Software Design (EMBD-SW) Fargo ND Register Description
Oct 16-18 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Schaumburg IL Full Description
Oct 16-17 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Duluth MN Full Description
Oct 16-17 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Sioux Falls SD Closed Description
Oct 21-22 Embedded Design with PetaLinux Tools (EMBD-PLNX) Naperville IL Full Description
Oct 21-21 SDSoC Development Environment and Methodology (EMBD-SDSOC) Orono (Minneapolis) MN Closed Description
Oct 21-23 Designing with VHDL (LANG-VHDL) Lincoln NE Closed Description
Oct 24-25 Designing with SystemVerilog (LANG-SVDES) Cedar Rapids IA Full Description
Oct 24-25 Zynq SoC System Architecture (EMBD-ZSA) Orono (Minneapolis) MN Register Description
Oct 24-25 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Fargo ND Full Description
Oct 28-29 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Schaumburg IL Register Description
Oct 28-28 Advanced Features and Techniques of Embedded Systems Software Design (EMBD-ADVSW) Lincoln NE Register Description
Oct 28-29 Embedded Design with PetaLinux Tools (EMBD-PLNX) Skakopee MN Register Description
Oct 31-Nov 1 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Schaumburg IL Register Description
Oct 31-Nov 1 Verification with SystemVerilog (LANG-SVVER) Brookings SD Register Description
Oct 31-Nov 1 DSP Design Using System Generator (DSP-SYSGEN) Cedar Rapids IA Register Description
November 2019
Nov 4-5 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Naperville IL Full Description

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Course Cancellation Policy

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