Course Schedule (updated frequently)
Date Course City State Register Description
May 2019
May 29-31 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Schaumburg IL Closed Description
June 2019
Jun 18-19 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Naperville IL Full Description
Jun 24-25 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
Jun 24-25 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Online Online Register Description
Jun 27-28 Verification with SystemVerilog (LANG-SVVER) Orono (Minneapolis) MN Register Description
July 2019
Jul 1-2 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Orono (Minneapolis) MN Register Description
Jul 8-10 Designing with VHDL (LANG-VHDL) Orono (Minneapolis) MN Register Description
Jul 8-10 Designing with VHDL (LANG-VHDL) Online Online Register Description
Jul 15-17 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Schaumburg IL Register Description
Jul 15-15 Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) Olathe KS Register Description
Jul 15-16 Embedded Systems Software Design (EMBD-SW) Sioux Falls SD Register Description
Jul 18-19 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Jul 18-19 Embedded Design with PetaLinux Tools (EMBD-PLNX) Fargo ND Register Description
Jul 18-19 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Madison WI Register Description
Jul 22-24 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Schaumburg IL Register Description
Jul 22-23 Designing with the 7 Series Families (FPGA-7SERIES) Brookings SD Register Description
Jul 22-23 Embedded Design with PetaLinux Tools (EMBD-PLNX) Cedar Rapids IA Register Description
Jul 25-26 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Jul 25-26 Advanced Features and Techniques of Embedded Systems Design (EMBD-ADVHW) Lincoln NE Register Description
Jul 25-26 Zynq SoC System Architecture (EMBD-ZSA) Milwaukee WI Register Description
Jul 29-30 DSP Design Using System Generator (DSP-SYSGEN) Schaumburg IL Register Description
Jul 29-30 Designing an Integrated PCI Express System (CONN-PCIE) Wichita KS Register Description
Jul 29-30 Advanced Features and Techniques of Embedded Systems Design (EMBD-ADVHW) Milwaukee WI Register Description
August 2019
Aug 1-1 SDSoC Development Environment and Methodology (EMBD-SDSOC) Schaumburg IL Register Description
Aug 1-2 DSP Design Using System Generator (DSP-SYSGEN) Olathe KS Register Description
Aug 1-2 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Duluth MN Register Description
Aug 5-6 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Aug 5-6 Advanced SDSoC Development Environment and Methodology (EMBD-ADVSDSOC) Springfield IL Register Description
Aug 5-7 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Sioux Falls SD Register Description
Aug 8-9 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Schaumburg IL Register Description
Aug 8-9 Advanced VHDL (LANG-ADVVHDL) Brookings SD Register Description
Aug 8-9 Designing an Integrated PCI Express System (CONN-PCIE) Omaha NE Register Description
Aug 12-12 Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) Orono (Minneapolis) MN Register Description
Aug 12-13 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Fargo ND Register Description
Aug 12-12 Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) Skakopee MN Register Description
Aug 13-14 Embedded Systems Design (EMBD-HW) Orono (Minneapolis) MN Register Description
Aug 14-16 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Duluth MN Register Description
Aug 15-16 Embedded Design with PetaLinux Tools (EMBD-PLNX) Schaumburg IL Register Description
Aug 19-20 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) Schaumburg IL Register Description
Aug 19-21 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Fargo ND Register Description
Aug 19-20 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Brookings SD Register Description
Aug 22-23 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Aug 22-23 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Lincoln NE Register Description
Aug 22-23 Designing an Integrated PCI Express System (CONN-PCIE) Madison WI Register Description
Aug 26-27 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
Aug 26-27 Designing with the 7 Series Families (FPGA-7SERIES) Cedar Rapids IA Register Description
Aug 26-28 Designing with VHDL (LANG-VHDL) Omaha NE Register Description
Aug 29-30 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Orono (Minneapolis) MN Register Description
Aug 29-30 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) Lemont IL Register Description
Aug 29-30 Vivado Design Suite for ISE PN Users (FPGA-V4ISE) Brookings SD Register Description
September 2019
Sep 2-3 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Orono (Minneapolis) MN Register Description
Sep 2-3 Vivado Design Suite Advanced XDC and STA for ISE Users (FPGA-VAXDC4ISE) Madison WI Register Description
Sep 2-4 Designing with Verilog (LANG-VERILOG) Omaha NE Register Description
Sep 4-6 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Cedar Rapids IA Register Description
Sep 5-6 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Orono (Minneapolis) MN Register Description
Sep 5-6 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Madison WI Register Description
November 2019
Nov 4-5 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Naperville IL Full Description

Student Cancellation Policy

  • Students cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
  • Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
  • Student cancellations must be sent here.

Course Cancellation Policy

  • We regret from time to time classes will need to be rescheduled or cancelled.
  • In the event of cancellation, live on-line training may be offered as a substitute.
  • Morgan Advanced Programmable Systems, Inc. may cancel a class up to 7 days before the scheduled start date of the class; all students will be entitled to a 100% refund.
  • Under no circumstances is Morgan Advanced Programmable Systems, Inc. responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.
  • For additional information or to schedule a private class contact us here.