Note: Courses can be run at your site, or at Morgan Advanced Programmable Systems, at Orono, MN, or at a conference room near you--for those companies that are allowing visitors. Please contact us at (952) 486-8881 or via this contact form.
Start | Days | Course | City | State | Register |
---|---|---|---|---|---|
02/01/2021 | 3 | Designing with Verilog (LANG-VERILOG) | Online | Online | Full |
02/04/2021 | 2 | Developing AI Inference Solutions with the Vitis AI Platform (AI-INFER) | Online | Online | Full |
02/04/2021 | 2 | Designing with SystemVerilog (LANG-SVDES) | Online | Online | Closed |
02/08/2021 | 2 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Online | Online | Register |
02/15/2021 | 1 | Developing Xilinx AI Solutions for Edge-based Applications (EMBD-AIEDGE) | Online | Online | Register |
02/16/2021 | 1 | UltraScale and UltraScale+ Architectures Workshop (FPGA-US1D) | Online | Online | Register |
02/17/2021 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Register |
02/22/2021 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Online | Online | Register |
02/23/2021 | 1 | Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) | Online | Online | Register |
02/24/2021 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Register |
02/24/2021 | 3 | Designing with VHDL (LANG-VHDL) | Online | Online | Register |
02/25/2021 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Register |
03/01/2021 | 2 | C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) | Online | Online | Full |
03/01/2021 | 2 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Online | Online | Register |
03/02/2021 | 2 | Zynq SoC System Architecture (EMBD-ZSA) | Saint Louis | MO | Register |
03/02/2021 | 2 | Zynq SoC System Architecture (EMBD-ZSA) | Online | Online | Register |
03/03/2021 | 2 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Orono (Minneapolis) | MN | Register |
03/03/2021 | 2 | Embedded Design with PetaLinux Tools (EMBD-PLNX) | Online | Online | Register |
03/03/2021 | 1 | Using Xilinx Alveo Cards to Accelerate Dynamic Workloads (FPGA-ALVEO) | Online | Online | Register |
03/04/2021 | 2 | Designing with Versal AI Engine 1 (ACAP-AIE1) | Orono (Minneapolis) | MN | Register |
03/04/2021 | 2 | Designing with Versal AI Engine 1 (ACAP-AIE1) | Online | Online | Register |
03/04/2021 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Online | Online | Register |
03/08/2021 | 2 | Designing with Versal AI Engine 2 (ACAP-AIE2) | Orono (Minneapolis) | MN | Register |
03/08/2021 | 2 | Designing with Versal AI Engine 2 (ACAP-AIE2) | Online | Online | Register |
03/08/2021 | 3 | Designing with the Versal ACAP: Architecture and Methodology (ACAP-ARCH) | Online | Online | Full |
03/08/2021 | 2 | Designing with Xilinx Serial Transceivers (CONN-TRX) | Online | Online | Register |
03/09/2021 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Online | Online | Register |
03/09/2021 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Bloomington | MN | Register |
03/10/2021 | 1 | Introduction to the Zynq SoC Architecture (INTRO-ZARCH) | Madison | WI | Register |
03/11/2021 | 2 | Designing with Versal AI Engine 3 (ACAP-AIE3) | Orono (Minneapolis) | MN | Soon |
03/11/2021 | 2 | Designing with Versal AI Engine 3 (ACAP-AIE3) | Online | Online | Soon |
03/11/2021 | 2 | Developing AI Inference Solutions with the Vitis AI Platform (AI-INFER) | Orono (Minneapolis) | MN | Register |
03/11/2021 | 2 | Developing AI Inference Solutions with the Vitis AI Platform (AI-INFER) | Online | Online | Register |
03/15/2021 | 3 | Designing with the Versal ACAP: Architecture and Methodology (ACAP-ARCH) | Orono (Minneapolis) | MN | Register |
03/15/2021 | 3 | Designing with the Versal ACAP: Architecture and Methodology (ACAP-ARCH) | Online | Online | Register |
03/17/2021 | 3 | Designing with Verilog (LANG-VERILOG) | Online | Online | Register |
03/19/2021 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Orono (Minneapolis) | MN | Register |
03/19/2021 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Online | Online | Register |
03/22/2021 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Overland Park | KS | Register |
03/24/2021 | 3 | Designing with VHDL (LANG-VHDL) | Orono (Minneapolis) | MN | Register |
03/24/2021 | 3 | Designing with VHDL (LANG-VHDL) | Online | Online | Register |
03/29/2021 | 2 | C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) | Orono (Minneapolis) | MN | Register |
03/29/2021 | 2 | C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) | Online | Online | Register |
03/29/2021 | 1 | Developing Xilinx AI Solutions for Edge-based Applications (EMBD-AIEDGE) | Online | Online | Register |
03/30/2021 | 2 | Embedded Systems Software Design (EMBD-SW) | Orono (Minneapolis) | MN | Register |
03/30/2021 | 2 | Embedded Systems Software Design (EMBD-SW) | Online | Online | Register |
04/01/2021 | 2 | Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) | Saint Louis | MO | Register |
04/01/2021 | 2 | Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) | Online | Online | Register |
04/01/2021 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Orono (Minneapolis) | MN | Register |
04/01/2021 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Online | Online | Register |
04/02/2021 | 1 | UltraScale and UltraScale+ Architectures Workshop (FPGA-US1D) | Saint Louis | MO | Register |
04/02/2021 | 1 | UltraScale and UltraScale+ Architectures Workshop (FPGA-US1D) | Online | Online | Register |
04/05/2021 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Orono (Minneapolis) | MN | Register |
04/05/2021 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Register |
04/05/2021 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Orono (Minneapolis) | MN | Register |
04/05/2021 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Register |
04/06/2021 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Orono (Minneapolis) | MN | Register |
04/06/2021 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Online | Online | Register |
04/07/2021 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Schaumburg | IL | Register |
04/07/2021 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Register |
04/07/2021 | 1 | Using Xilinx Alveo Cards to Accelerate Dynamic Workloads (FPGA-ALVEO) | Orono (Minneapolis) | MN | Register |
04/07/2021 | 1 | Using Xilinx Alveo Cards to Accelerate Dynamic Workloads (FPGA-ALVEO) | Online | Online | Register |
04/08/2021 | 2 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Orono (Minneapolis) | MN | Register |
04/08/2021 | 2 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Online | Online | Register |
04/12/2021 | 2 | Designing with Versal AI Engine 1 (ACAP-AIE1) | Schaumburg | IL | Register |
04/12/2021 | 2 | Designing with Versal AI Engine 1 (ACAP-AIE1) | Online | Online | Register |
04/12/2021 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Orono (Minneapolis) | MN | Register |
04/12/2021 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Online | Online | Register |
04/12/2021 | 3 | Designing with VHDL (LANG-VHDL) | Online | Online | Register |
04/13/2021 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Orono (Minneapolis) | MN | Register |
04/13/2021 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Register |
04/14/2021 | 2 | Designing with Versal AI Engine 2 (ACAP-AIE2) | Schaumburg | IL | Register |
04/14/2021 | 2 | Designing with Versal AI Engine 2 (ACAP-AIE2) | Online | Online | Register |
04/15/2021 | 2 | DSP Design Using System Generator (DSP-SYSGEN) | Orono (Minneapolis) | MN | Register |
04/15/2021 | 2 | DSP Design Using System Generator (DSP-SYSGEN) | Online | Online | Register |
04/15/2021 | 2 | Advanced VHDL (LANG-ADVVHDL) | Online | Online | Register |
04/16/2021 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Schaumburg | IL | Register |
04/16/2021 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Online | Online | Register |
04/19/2021 | 2 | Designing with Versal AI Engine 1 (ACAP-AIE1) | Saint Louis | MO | Register |
04/19/2021 | 2 | Designing with Versal AI Engine 3 (ACAP-AIE3) | Schaumburg | IL | Soon |
04/19/2021 | 2 | Designing with Versal AI Engine 3 (ACAP-AIE3) | Online | Online | Soon |
04/19/2021 | 2 | Developing AI Inference Solutions with the Vitis AI Platform (AI-INFER) | Online | Online | Register |
04/19/2021 | 2 | Developing AI Inference Solutions with the Vitis AI Platform (AI-INFER) | Naperville | IL | Register |
04/21/2021 | 2 | Designing with Versal AI Engine 2 (ACAP-AIE2) | Saint Louis | MO | Register |
04/21/2021 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Orono (Minneapolis) | MN | Register |
04/21/2021 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Register |
04/21/2021 | 1 | Developing Xilinx AI Solutions for Edge-based Applications (EMBD-AIEDGE) | Schaumburg | IL | Register |
04/21/2021 | 1 | Developing Xilinx AI Solutions for Edge-based Applications (EMBD-AIEDGE) | Online | Online | Register |
04/22/2021 | 2 | Embedded Systems Design (EMBD-HW) | Orono (Minneapolis) | MN | Register |
04/22/2021 | 2 | Embedded Systems Design (EMBD-HW) | Online | Online | Register |
04/23/2021 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Saint Louis | MO | Register |
04/26/2021 | 2 | Designing with Versal AI Engine 3 (ACAP-AIE3) | Schaumburg | IL | Soon |
04/26/2021 | 2 | Designing with Versal AI Engine 3 (ACAP-AIE3) | Online | Online | Soon |
04/26/2021 | 2 | Designing with Xilinx Serial Transceivers (CONN-TRX) | Naperville | IL | Register |
04/28/2021 | 3 | Designing with the Versal ACAP: Architecture and Methodology (ACAP-ARCH) | Schaumburg | IL | Register |
04/28/2021 | 3 | Designing with the Versal ACAP: Architecture and Methodology (ACAP-ARCH) | Online | Online | Register |
05/03/2021 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Online | Online | Register |
05/03/2021 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Hoffman Estates | IL | Register |
05/03/2021 | 2 | Developing Multimedia Solutions with the Video Codec Unit Using the GStreamer Framework (EMBD-MMEDIA) | Orono (Minneapolis) | MN | Soon |
05/03/2021 | 2 | Developing Multimedia Solutions with the Video Codec Unit Using the GStreamer Framework (EMBD-MMEDIA) | Online | Online | Soon |
05/04/2021 | 2 | Embedded Systems Software Design (EMBD-SW) | Schaumburg | IL | Register |
05/04/2021 | 2 | Embedded Systems Software Design (EMBD-SW) | Online | Online | Register |
05/06/2021 | 2 | Embedded Systems Design (EMBD-HW) | Schaumburg | IL | Register |
05/06/2021 | 2 | Embedded Systems Design (EMBD-HW) | Online | Online | Register |
05/10/2021 | 2 | Designing with Versal AI Engine 1 (ACAP-AIE1) | Online | Online | Register |
05/10/2021 | 2 | Designing with Versal AI Engine 1 (ACAP-AIE1) | Olathe | KS | Register |
05/10/2021 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Schaumburg | IL | Register |
05/10/2021 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Register |
05/10/2021 | 1 | Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) | Online | Online | Register |
05/11/2021 | 2 | Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) | Online | Online | Register |
05/12/2021 | 2 | Designing with Versal AI Engine 2 (ACAP-AIE2) | Online | Online | Register |
05/12/2021 | 2 | Designing with Versal AI Engine 2 (ACAP-AIE2) | Online | Online | Register |
05/12/2021 | 2 | Designing with Versal AI Engine 2 (ACAP-AIE2) | Olathe | KS | Register |
05/12/2021 | 2 | Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) | Online | Online | Register |
05/14/2021 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Online | Online | Register |
05/14/2021 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Olathe | KS | Register |
05/17/2021 | 2 | Designing with Xilinx Serial Transceivers (CONN-TRX) | Orono (Minneapolis) | MN | Register |
05/17/2021 | 2 | Designing with Xilinx Serial Transceivers (CONN-TRX) | Online | Online | Register |
05/17/2021 | 2 | Developing Multimedia Solutions with the Video Codec Unit Using the GStreamer Framework (EMBD-MMEDIA) | Orono (Minneapolis) | MN | Soon |
05/17/2021 | 3 | Designing with VHDL (LANG-VHDL) | Orono (Minneapolis) | MN | Register |
05/17/2021 | 3 | Designing with VHDL (LANG-VHDL) | Online | Online | Register |
05/18/2021 | 2 | Designing with the 7 Series Families (FPGA-7SERIES) | Orono (Minneapolis) | MN | Register |
05/18/2021 | 2 | Designing with the 7 Series Families (FPGA-7SERIES) | Online | Online | Register |
05/19/2021 | 2 | Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) | Orono (Minneapolis) | MN | Register |
05/19/2021 | 2 | Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) | Online | Online | Register |
05/21/2021 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Schaumburg | IL | Register |
05/21/2021 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Online | Online | Register |
06/03/2021 | 2 | Designing with Versal AI Engine 1 (ACAP-AIE1) | Saint Louis | MO | Register |
06/07/2021 | 3 | Designing with the Versal ACAP: Architecture and Methodology (ACAP-ARCH) | Saint Louis | MO | Register |
06/07/2021 | 2 | Designing with SystemVerilog (LANG-SVDES) | Orono (Minneapolis) | MN | Register |
06/07/2021 | 2 | Designing with SystemVerilog (LANG-SVDES) | Online | Online | Register |
06/10/2021 | 2 | Designing with Versal AI Engine 2 (ACAP-AIE2) | Saint Louis | MO | Register |
06/10/2021 | 2 | Designing with Versal AI Engine 2 (ACAP-AIE2) | Online | Online | Register |
06/14/2021 | 2 | Designing with Versal AI Engine 3 (ACAP-AIE3) | Saint Louis | MO | Soon |
06/14/2021 | 2 | Developing AI Inference Solutions with the Vitis AI Platform (AI-INFER) | Saint Louis | MO | Register |
06/16/2021 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Saint Louis | MO | Register |
Don't see a class?
If you do not see a class that you're interested in on the schedule, please either give us a call or contact us. We will work to rearrange the schedule so that key members of your team can get the Xilinx training they need as soon as possible.
Cancellation Policies
These are our cancellation policies:
Student Cancellation Policy
- Students cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
- Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
- Student cancellations must be sent here.
Course Cancellation Policy
- We regret that from time to time classes will need to be rescheduled or cancelled.
- In the event of cancellation, live on-line training may be offered as a substitute.
- Morgan Advanced Programmable Systems, Inc. may cancel a class up to 7 days before the scheduled start date of the class; all students will be entitled to a 100% refund.
- Under no circumstances is Morgan Advanced Programmable Systems, Inc. responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.
- For additional information or to schedule a private class contact us here.