Note: Courses can be run at your site, or at Morgan Advanced Programmable Systems, at Orono, MN, or at a conference room near you--for those companies that are allowing visitors. Please contact us at (952) 486-8881 or via this contact form.
Start | Days | Course | City | State | Register |
---|---|---|---|---|---|
09/03/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Orono (Minneapolis) | MN | Full |
09/03/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Full |
09/05/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Orono (Minneapolis) | MN | Closed |
09/05/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Online | Online | Closed |
09/09/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Schaumburg | IL | Closed |
09/09/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Orono (Minneapolis) | MN | Full |
09/09/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Online | Online | Full |
09/11/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Orono (Minneapolis) | MN | Register |
09/11/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Register |
09/12/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Orono (Minneapolis) | MN | Register |
09/12/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Online | Online | Register |
09/12/2024 | 2 | DSP Design Using System Generator (DSP-SYSGEN) | Orono (Minneapolis) | MN | Register |
09/12/2024 | 2 | DSP Design Using System Generator (DSP-SYSGEN) | Online | Online | Register |
09/12/2024 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Orono (Minneapolis) | MN | Register |
09/12/2024 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Online | Online | Register |
09/17/2024 | 2 | Designing with Versal AI Engine 3 Kernel Programming and Optimization (ACAP-AIE3) | Olathe | KS | Closed |
09/17/2024 | 3 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Schaumburg | IL | Closed |
09/17/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Orono (Minneapolis) | MN | Full |
09/17/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Online | Online | Full |
09/17/2024 | 3 | Designing with VHDL (LANG-VHDL) | Orono (Minneapolis) | MN | Register |
09/17/2024 | 3 | Designing with VHDL (LANG-VHDL) | Online | Online | Register |
09/18/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Orono (Minneapolis) | MN | Register |
09/18/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Online | Online | Register |
09/18/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Hoffman Estates | IL | Closed |
09/18/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Hoffman Estates | IL | Closed |
09/18/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Hoffman Estates | IL | Closed |
09/19/2024 | 2 | Designing with Versal AI Engine 3 Kernel Programming and Optimization (ACAP-AIE3) | Olathe | KS | Full |
09/23/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Schaumburg | IL | Register |
09/23/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Register |
09/23/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Orono (Minneapolis) | MN | Register |
09/23/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Online | Online | Register |
09/24/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Orono (Minneapolis) | MN | Register |
09/24/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Online | Online | Register |
09/24/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Orono (Minneapolis) | MN | Register |
09/24/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Online | Online | Register |
09/25/2024 | 2 | Designing with Versal AI Engine 1 Architecture and Design Flow (ACAP-AIE1) | Schaumburg | IL | Register |
09/25/2024 | 2 | Designing with Versal AI Engine 1 Architecture and Design Flow (ACAP-AIE1) | Online | Online | Register |
09/25/2024 | 2 | High-Level Synthesis with the Vitis HLS Tool (DSP-HLS) | Orono (Minneapolis) | MN | Register |
09/25/2024 | 2 | High-Level Synthesis with the Vitis HLS Tool (DSP-HLS) | Online | Online | Register |
09/30/2024 | 1 | Designing with the Versal ACAP: Power and Board Design (ACAP-POWER-BD) | Orono (Minneapolis) | MN | Register |
09/30/2024 | 1 | Designing with the Versal ACAP: Power and Board Design (ACAP-POWER-BD) | Online | Online | Register |
09/30/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Overland Park | KS | Register |
10/02/2024 | 2 | Designing with Versal AI Engine 2 Graph Programming with AI Engine Kernels (ACAP-AIE2) | Orono (Minneapolis) | MN | Register |
10/02/2024 | 2 | Designing with Versal AI Engine 2 Graph Programming with AI Engine Kernels (ACAP-AIE2) | Online | Online | Register |
10/07/2024 | 2 | Designing with Versal AI Engine 3 Kernel Programming and Optimization (ACAP-AIE3) | Online | Online | Register |
10/07/2024 | 2 | Designing with Versal AI Engine 3 Kernel Programming and Optimization (ACAP-AIE3) | Fargo | ND | Register |
10/07/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Overland Park | KS | Register |
10/08/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Online | Online | Register |
10/08/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Olathe | KS | Register |
10/09/2024 | 3 | Designing with the Versal ACAP: Architecture and Methodology (ACAP-ARCH) | Orono (Minneapolis) | MN | Register |
10/09/2024 | 3 | Designing with the Versal ACAP: Architecture and Methodology (ACAP-ARCH) | Online | Online | Register |
10/09/2024 | 2 | High-Level Synthesis with the Vitis HLS Tool (DSP-HLS) | Orono (Minneapolis) | MN | Register |
10/09/2024 | 2 | High-Level Synthesis with the Vitis HLS Tool (DSP-HLS) | Online | Online | Register |
10/14/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Naperville | IL | Register |
10/14/2024 | 1 | Designing with the Versal ACAP: Power and Board Design (ACAP-POWER-BD) | Naperville | IL | Register |
10/14/2024 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Orono (Minneapolis) | MN | Register |
10/14/2024 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Register |
10/15/2024 | 3 | Designing with VHDL (LANG-VHDL) | Online | Online | Register |
10/15/2024 | 3 | Designing with VHDL (LANG-VHDL) | Olathe | KS | Register |
10/16/2024 | 3 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Orono (Minneapolis) | MN | Register |
10/16/2024 | 3 | Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) | Online | Online | Register |
10/16/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Orono (Minneapolis) | MN | Register |
10/16/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Register |
10/17/2024 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Orono (Minneapolis) | MN | Register |
10/17/2024 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Online | Online | Register |
10/21/2024 | 2 | Designing with Versal AI Engine 1 Architecture and Design Flow (ACAP-AIE1) | Online | Online | Register |
10/21/2024 | 2 | Designing with Versal AI Engine 1 Architecture and Design Flow (ACAP-AIE1) | Fargo | ND | Register |
10/21/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Saint Louis | MO | Register |
10/22/2024 | 2 | Designing with Versal AI Engine 2 Graph Programming with AI Engine Kernels (ACAP-NOC) | Fargo | ND | Register |
10/28/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Orono (Minneapolis) | MN | Register |
10/28/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Online | Online | Register |
10/29/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Register |
10/29/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Champaign-Urbana | IL | Register |
10/30/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Orono (Minneapolis) | MN | Register |
10/30/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Register |
10/31/2024 | 2 | DSP Design Using System Generator (DSP-SYSGEN) | Online | Online | Register |
10/31/2024 | 2 | DSP Design Using System Generator (DSP-SYSGEN) | Champaign-Urbana | IL | Register |
11/05/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Online | Online | Register |
11/05/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Hoffman Estates | IL | Register |
11/06/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Saint Louis | MO | Register |
11/07/2024 | 2 | Designing with Versal AI Engine 2 Graph Programming with AI Engine Kernels (ACAP-AIE2) | Fargo | ND | Register |
11/07/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Orono (Minneapolis) | MN | Register |
11/07/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Register |
11/11/2024 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Orono (Minneapolis) | MN | Register |
11/11/2024 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Online | Online | Register |
11/12/2024 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Orono (Minneapolis) | MN | Register |
11/12/2024 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Register |
11/13/2024 | 1 | Introduction to AMD Versal Adaptive SoC (ASOC-INTRO) | Online | Online | Register |
11/13/2024 | 2 | DSP Design Using System Generator (DSP-SYSGEN) | Orono (Minneapolis) | MN | Register |
11/13/2024 | 2 | DSP Design Using System Generator (DSP-SYSGEN) | Online | Online | Register |
11/13/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Orono (Minneapolis) | MN | Register |
11/13/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Register |
11/14/2024 | 2 | Designing with Versal AI Engine 3 Kernel Programming and Optimization (ACAP-AIE3) | Olathe | KS | Register |
11/18/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Schaumburg | IL | Register |
11/18/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Register |
11/18/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Orono (Minneapolis) | MN | Register |
11/18/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Online | Online | Register |
11/19/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Orono (Minneapolis) | MN | Register |
11/19/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Online | Online | Register |
11/19/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Orono (Minneapolis) | MN | Register |
11/19/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Online | Online | Register |
Don't see a class?
If you do not see a class that you're interested in on the schedule, please either give us a call or contact us. We will work to rearrange the schedule so that key members of your team can get the Xilinx training they need as soon as possible.
Cancellation Policies
These are our cancellation policies:
Student Cancellation Policy
- Students cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
- Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
- Student cancellations must be sent here.
Course Cancellation Policy
- We regret that from time to time classes will need to be rescheduled or cancelled.
- In the event of cancellation, live on-line training may be offered as a substitute.
- Morgan Advanced Programmable Systems, Inc. may cancel a class up to 7 days before the scheduled start date of the class; all students will be entitled to a 100% refund.
- Under no circumstances is Morgan Advanced Programmable Systems, Inc. responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.
- For additional information or to schedule a private class contact us here.