Course Schedule (updated frequently)
Date Course City State Register Description
December 2018
Dec 3-4 Advanced SDSoC Development Environment and Methodology (EMBD-ADVSDSOC) Orono (Minneapolis) MN Register Description
Dec 3-4 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) Orono (Minneapolis) MN Register Description
Dec 5-6 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Dec 6-7 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) Overland Park KS Register Description
Dec 6-7 Designing with the 7 Series Families (FPGA-7SERIES) Wichita KS Register Description
Dec 10-11 Embedded Design with PetaLinux Tools (EMBD-PLNX) St. Louis MO Register Description
Dec 10-11 Designing FPGAs using the Vivado Design Suite 3 (FPGA-VDES3) Orono (Minneapolis) MN Register Description
Dec 12-14 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Orono (Minneapolis) MN Register Description
Dec 17-18 Designing FPGAs using the Vivado Design Suite 1 (FPGA-VDES1) Madison WI Register Description
Dec 17-18 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Cedar Rapids IA Register Description
Dec 19-21 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Madison WI Register Description
Dec 20-21 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) St. Louis MO Register Description
Dec 27-28 Embedded Design with PetaLinux Tools (EMBD-PLNX) Orono (Minneapolis) MM Register Description
January 2019
Jan 7-9 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) CedarRapids IA Register Description
Jan 10-11 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) CedarRapids IA Register Description
Jan 17-18 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Wichita KS Register Description
Jan 21-22 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
February 2019
Feb 4-5 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Feb 4-5 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Feb 4-6 Designing with VHDL (LANG-VHDL) Olathe KS Register Description
Feb 7-8 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Schaumburg IL Register Description
Feb 7-8 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Schaumburg IL Register Description
Feb 7-8 Designing FPGAs using the Vivado Design Suite 1 (FPGA-VDES1) Milwaukee WI Register Description
Feb 7-8 Advanced VHDL (LANG-ADVVHDL) Olathe KS Register Description
Feb 11-12 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Feb 14-15 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Schaumburg IL Register Description

Student Cancellation Policy

  • Students cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
  • Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
  • Student cancellations must be sent here.

Course Cancellation Policy

  • We regret from time to time classes will need to be rescheduled or cancelled.
  • In the event of cancellation, live on-line training may be offered as a substitute.
  • Morgan Advanced Programmable Systems, Inc. may cancel a class up to 7 days before the scheduled start date of the class; all students will be entitled to a 100% refund.
  • Under no circumstances is Morgan Advanced Programmable Systems, Inc. responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.
  • For additional information or to schedule a private class contact us here.