February 2020
Feb 20-21 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Feb 20-21 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs (EMBD-OCLSDA) Orono (Minneapolis) MN Register Description
Feb 20-21 Designing with SystemVerilog (LANG-SVDES) Orono (Minneapolis) MN Register Description
Feb 24-25 Embedded Design with PetaLinux Tools (EMBD-PLNX) Orono (Minneapolis) MN Register Description
Feb 24-25 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) Orono (Minneapolis) MN Register Description
Feb 24-26 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Schaumburg IL Register Description
Feb 25-25 Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) Orono (Minneapolis) MN Full Description
Feb 27-27 Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) Orono (Minneapolis) MN Register Description
Feb 27-28 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Feb 27-28 Verification with SystemVerilog (LANG-SVVER) Orono (Minneapolis) MN Register Description
March 2020
Mar 2-3 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Schaumburg IL Full Description
Mar 2-3 Embedded Systems Software Design (EMBD-SW) Overland Park KS Register Description
Mar 5-6 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Schaumburg IL Full Description
Mar 5-6 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Overland Park KS Register Description
Mar 9-10 Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) Orono (Minneapolis) MN Register Description
Mar 9-10 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Schaumburg IL Register Description
Mar 9-10 Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) Overland Park KS Full Description
Mar 10-11 Embedded Systems Software Design (EMBD-SW) Orono (Minneapolis) MN Register Description
Mar 12-13 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Schaumburg IL Register Description
Mar 13-13 Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) Orono (Minneapolis) MN Register Description
Mar 16-18 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Bloomington MN Register Description
Mar 17-19 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Orono (Minneapolis) MN Register Description
Mar 23-24 Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) Schaumburg IL Register Description
Mar 23-25 Designing with Verilog (LANG-VERILOG) Orono (Minneapolis) MN Register Description
Mar 24-25 Embedded Systems Software Design (EMBD-SW) Schaumburg IL Register Description
Mar 25-26 Designing with SystemVerilog (LANG-SVDES) Orono (Minneapolis) MN Register Description
Mar 25-25 Vitis Introduction Workshop (VITIS-1D) Fargo ND Register Description
Mar 27-27 Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) Schaumburg IL Register Description
April 2020
Apr 2-2 Vitis Introduction Workshop (VITIS-1D) Hoffman Estates IL Register Description
Apr 6-7 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
Apr 6-7 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Schaumburg IL Register Description
Apr 8-8 Vitis Introduction Workshop (VITIS-1D) Bloomington MN Register Description
Apr 9-10 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Orono (Minneapolis) MN Register Description
Apr 13-14 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Orono (Minneapolis) MN Register Description
Apr 16-17 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Orono (Minneapolis) MN Register Description
Apr 16-16 Vitis Introduction Workshop (VITIS-1D) Cedar Rapids IA Register Description
Apr 20-21 Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) Saint Louis MO Register Description
Apr 20-22 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Schaumburg IL Register Description
Apr 20-21 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Apr 20-24 Zynq MPSoC Master Training for Experienced FPGA Engineers (EMBD-33040) Orono (Minneapolis) MN Register Description
Apr 20-21 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Schaumburg IL Register Description
Apr 20-21 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Saint Louis MO Register Description
Apr 21-22 Embedded Systems Software Design (EMBD-SW) Saint Louis MO Register Description
Apr 21-23 Designing with VHDL (LANG-VHDL) Schaumburg IL Register Description
Apr 22-24 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Orono (Minneapolis) MN Register Description
Apr 23-24 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Saint Louis MO Register Description
Apr 24-24 Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) Saint Louis MO Register Description
Apr 27-28 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Apr 27-29 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Schaumburg IL Register Description
May 2020
May 4-6 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Schaumburg IL Register Description
May 4-5 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Schaumburg IL Register Description
May 4-5 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
May 7-8 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Schaumburg IL Register Description
May 7-8 Embedded Design with PetaLinux Tools (EMBD-PLNX) Orono (Minneapolis) MN Register Description
May 11-12 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Schaumburg IL Register Description
May 14-15 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Schaumburg IL Register Description
May 18-19 Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) Overland Park KS Register Description
May 18-20 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Orono (Minneapolis) MN Register Description
May 18-22 Zynq MPSoC Master Training for Experienced FPGA Engineers (EMBD-33040) Orono (Minneapolis) MN Register Description
May 19-20 Embedded Systems Software Design (EMBD-SW) Overland Park KS Register Description
May 20-21 Embedded Design with PetaLinux Tools (EMBD-PLNX) Overland Park KS Register Description
May 22-22 Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) Overland Park KS Register Description
May 25-27 Designing with VHDL (LANG-VHDL) Schaumburg IL Register Description
May 28-29 Advanced VHDL (LANG-ADVVHDL) Schaumburg IL Register Description
June 2020
Jun 1-2 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Saint Louis MO Register Description
Jun 3-5 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Schaumburg IL Register Description
Jun 4-5 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Saint Louis MO Register Description
Jun 8-9 Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) Orono (Minneapolis) MN Register Description
Jun 8-9 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Saint Louis MO Register Description
Jun 9-10 Embedded Systems Software Design (EMBD-SW) Orono (Minneapolis) MN Register Description
Jun 10-11 Embedded Design with PetaLinux Tools (EMBD-PLNX) Orono (Minneapolis) MN Register Description
Jun 11-12 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Saint Louis MO Register Description
Jun 12-12 Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) Orono (Minneapolis) MN Register Description
Jun 15-16 Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) Schaumburg IL Register Description
Jun 16-17 Embedded Systems Software Design (EMBD-SW) Schaumburg IL Register Description
Jun 17-18 Embedded Design with PetaLinux Tools (EMBD-PLNX) Schaumburg IL Register Description
Jun 19-19 Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) Schaumburg IL Register Description
Jun 22-24 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Schaumburg IL Register Description
Jun 29-Jul 1 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Orono (Minneapolis) MN Register Description
July 2020
Jul 6-8 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Schaumburg IL Register Description
Jul 9-10 Embedded Design with PetaLinux Tools (EMBD-PLNX) Schaumburg IL Register Description
Jul 13-15 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Saint Louis MO Register Description
Jul 15-17 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Saint Louis MO Register Description
August 2020
Aug 3-5 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Orono (Minneapolis) MN Register Description
Aug 6-7 Embedded Design with PetaLinux Tools (EMBD-PLNX) Orono (Minneapolis) MN Register Description
Aug 10-12 Designing with VHDL (LANG-VHDL) Orono (Minneapolis) MN Register Description
Aug 10-11 Accelerating Applications with the Vitis Unified Software Environment (AI-ACCEL) Schaumburg IL Register Description
Aug 13-14 Advanced VHDL (LANG-ADVVHDL) Orono (Minneapolis) MN Register Description
Aug 13-13 Migrating to the Vitis Embedded Software Development IDE workshop (EMBD-VITIS) Schaumburg IL Register Description

Don't see a class?

If you do not see a class that you're interested in on the schedule, please either give us a call, or contact us.  We will work to rearranged the schedule so that key members of your team can get the Xilinx training they need as soon as possible.

Student Cancellation Policy

  • Students cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
  • Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
  • Student cancellations must be sent here.

Course Cancellation Policy

  • We regret from time to time classes will need to be rescheduled or cancelled.
  • In the event of cancellation, live on-line training may be offered as a substitute.
  • Morgan Advanced Programmable Systems, Inc. may cancel a class up to 7 days before the scheduled start date of the class; all students will be entitled to a 100% refund.
  • Under no circumstances is Morgan Advanced Programmable Systems, Inc. responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.
  • For additional information or to schedule a private class contact us here.