Course Schedule (updated frequently)

Date Course City State Register Description
January 2019
Jan 7-9 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Cedar Rapids IA Register Description
Jan 10-11 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) Cedar Rapids IA Register Description
Jan 17-18 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Wichita KS Register Description
Jan 21-22 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) Schaumburg IL Register Description
Jan 23-24 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) SaintLouis MO Register Description
Jan 28-30 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Orono (Minneapolis) MN Register Description
Jan 31-Feb 1 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
February 2019
Feb 4-6 Designing with VHDL (LANG-VHDL) Bloomington MN Register Description
Feb 4-5 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Feb 4-5 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Milwaukee WI Register Description
Feb 4-6 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Schaumburg IL Register Description
Feb 6-6 SDSoC Development Environment and Methodology (EMBD-SDSOC) Orono (Minneapolis) MN Register Description
Feb 6-8 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Schaumburg IL Register Description
Feb 7-8 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Schaumburg IL Register Description
Feb 7-8 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Milwaukee WI Register Description
Feb 7-8 Advanced VHDL (LANG-ADVVHDL) Overland Park KS Register Description
Feb 11-13 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Orono (Minneapolis) MN Register Description
Feb 11-12 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Cedar Rapids IA Register Description
Feb 11-13 Designing with Verilog (LANG-VERILOG) Schaumburg IL Register Description
Feb 11-13 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Online Online Register Description
Feb 14-15 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Online Online Register Description
Feb 14-15 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
Feb 18-20 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Orono (Minneapolis) MN Register Description
Feb 18-18 Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) Overland Park KS Register Description
Feb 18-19 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Feb 18-20 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Online Online Register Description
Feb 20-21 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Schaumburg IL Register Description
Feb 21-22 Designing with SystemVerilog (LANG-SVDES) Schaumburg IL Register Description
Feb 21-22 Designing with SystemVerilog (LANG-SVDES) Online Online Register Description
Feb 25-26 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Lemont IL Register Description
Feb 28-Mar 1 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Orono (Minneapolis) MN Register Description
Feb 28-Mar 1 Xilinx Partial Reconfiguration Tools and Techniques (FPGA-PR) Wichita KS Register Description
Feb 28-Mar 1 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Online Online Register Description
March 2019
Mar 4-6 Designing with VHDL (LANG-VHDL) Orono (Minneapolis) MN Register Description
Mar 4-6 Designing with VHDL (LANG-VHDL) Online Online Register Description
Mar 4-5 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Overland Park KS Register Description
Mar 5-6 Advanced SDSoC Development Environment and Methodology (EMBD-ADVSDSOC) Orono (Minneapolis) MN Register Description
Mar 7-8 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Overland Park KS Register Description
Mar 7-8 Advanced VHDL (LANG-ADVVHDL) SaintLouis MO Register Description
Mar 11-13 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Schaumburg IL Register Description
Mar 11-11 Advanced Features and Techniques of Embedded Systems Software Design (EMBD-ADVSW) Overland Park KS Register Description
Mar 11-12 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Mar 11-13 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Online Online Register Description
Mar 14-15 Zynq SoC System Architecture (EMBD-ZSA) Schaumburg IL Register Description
Mar 14-15 Embedded Systems Software Design (EMBD-SW) Bloomington MN Register Description
Mar 14-15 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Orono (Minneapolis) MN Register Description
Mar 18-20 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Orono (Minneapolis) MN Register Description
Mar 18-19 Embedded Systems Software Design (EMBD-SW) Schaumburg IL Register Description
Mar 18-19 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Brookings SD Register Description
Mar 18-20 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Online Online Register Description
Mar 20-22 Designing with Verilog (LANG-VERILOG) Overland Park KS Register Description
Mar 20-20 Advanced Features and Techniques of Embedded Systems Software Design (EMBD-ADVSW) Schaumburg IL Register Description
Mar 20-20 SDSoC Development Environment and Methodology (EMBD-SDSOC) Brookings SD Register Description
Mar 21-22 Embedded Design with PetaLinux Tools (EMBD-PLNX) Schaumburg IL Register Description
Mar 21-22 Advanced SDSoC Development Environment and Methodology (EMBD-ADVSDSOC) Brookings SD Register Description
Mar 25-27 Designing with VHDL (LANG-VHDL) Naperville IL Register Description
Mar 25-27 Designing with Verilog (LANG-VERILOG) Wichita KS Register Description
Mar 25-25 SDSoC Development Environment and Methodology (EMBD-SDSOC) Schaumburg IL Register Description
Mar 26-27 Advanced SDSoC Development Environment and Methodology (EMBD-ADVSDSOC) Schaumburg IL Register Description
Mar 28-29 Designing with SystemVerilog (LANG-SVDES) Wichita KS Register Description
Mar 28-29 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Schaumburg IL Register Description
April 2019
Apr 1-3 Designing with VHDL (LANG-VHDL) Orono (Minneapolis) MN Register Description
Apr 1-3 Designing with VHDL (LANG-VHDL) Online Online Register Description
Apr 4-5 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Apr 4-5 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Schaumburg IL Register Description
Apr 4-5 Zynq SoC System Architecture (EMBD-ZSA) Madison WI Register Description
Apr 8-9 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Schaumburg IL Register Description
Apr 8-9 Zynq SoC System Architecture (EMBD-ZSA) Wichita KS Register Description
Apr 8-9 Essential DSP Implementation Techniques for Xilinx FPGAs (DSP-ESS) SaintLouis MO Register Description
Apr 10-12 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Schaumburg IL Register Description
Apr 11-12 DSP Design Using System Generator (DSP-SYSGEN) Overland Park KS Register Description
Apr 11-12 Embedded Design with PetaLinux Tools (EMBD-PLNX) Madison WI Register Description
Apr 11-12 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Schaumburg IL Register Description
Apr 15-17 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Orono (Minneapolis) MN Register Description
Apr 15-17 Designing with Verilog (LANG-VERILOG) Cedar Rapids IA Register Description
Apr 15-16 Embedded Systems Software Design (EMBD-SW) SiouxFalls SD Register Description
Apr 15-17 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Online Online Register Description
Apr 18-19 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) SaintLouis MO Register Description
Apr 18-19 DSP Design Using System Generator (DSP-SYSGEN) Wichita KS Register Description
Apr 22-24 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Schaumburg IL Register Description
Apr 22-23 DSP Design Using System Generator (DSP-SYSGEN) Brookings SD Register Description
Apr 22-22 Developing AWS F1 Applications Using the SDAccel Environment (EMBD-AWS) Wichita KS Register Description
Apr 22-24 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Online Online Register Description
Apr 25-26 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Apr 25-26 DSP Design Using System Generator (DSP-SYSGEN) Omaha NE Register Description
Apr 29-30 Verification with SystemVerilog (LANG-SVVER) Orono (Minneapolis) MN Register Description
Apr 29-29 Essentials of Microprocessors (EMBD11000) Springfield IL Register Description
May 2019
May 1-2 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
May 6-7 Verification with SystemVerilog (LANG-SVVER) Orono (Minneapolis) MN Register Description

Student Cancellation Policy

  • Students cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
  • Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
  • Student cancellations must be sent here.

Course Cancellation Policy

  • We regret from time to time classes will need to be rescheduled or cancelled.
  • In the event of cancellation, live on-line training may be offered as a substitute.
  • Morgan Advanced Programmable Systems, Inc. may cancel a class up to 7 days before the scheduled start date of the class; all students will be entitled to a 100% refund.
  • Under no circumstances is Morgan Advanced Programmable Systems, Inc. responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.
  • For additional information or to schedule a private class contact us here.