September 2019
Sep 23-24 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
October 2019
Oct 2-4 Designing with VHDL (LANG-VHDL) Orono (Minneapolis) MN Register Description
Oct 3-4 Verification with SystemVerilog (LANG-SVVER) Orono (Minneapolis) MN Register Description
Oct 3-4 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Oct 7-8 Xilinx Partial Reconfiguration Tools and Techniques (FPGA-PR) Overland Park KS Register Description
Oct 7-8 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Oct 7-8 How to Design a High-Speed Memory Interface (Legacy Vivado 2015_1) (CONN-MIF) Orono (Minneapolis) MN Register Description
Oct 9-11 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Orono (Minneapolis) MN Register Description
Oct 10-11 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Orono (Minneapolis) MN Register Description
Oct 14-16 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Orono (Minneapolis) MN Register Description
Oct 14-15 DSP Design Using System Generator (DSP-SYSGEN) Orono (Minneapolis) MN Register Description
Oct 16-17 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs (EMBD-OCLSDA) Chicago IL Register Description
Oct 17-18 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Oct 17-18 Designing with SystemVerilog (LANG-SVDES) Orono (Minneapolis) MN Register Description
Oct 21-22 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
Oct 24-25 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Orono (Minneapolis) MN Register Description
Oct 28-28 Advanced Features and Techniques of Embedded Systems Software Design (EMBD-ADVSW) Orono (Minneapolis) MN Register Description
Oct 28-29 Advanced VHDL (LANG-ADVVHDL) Orono (Minneapolis) MN Register Description
Oct 31-Nov 1 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Orono (Minneapolis) MN Register Description
Oct 31-Nov 1 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs (EMBD-OCLSDA) Orono (Minneapolis) MN Register Description
Oct 31-Nov 1 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Schaumburg IL Register Description
November 2019
Nov 4-5 Verification with SystemVerilog (LANG-SVVER) Naperville IL Register Description
Nov 4-5 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Nov 6-8 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Schaumburg IL Register Description
Nov 7-8 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Orono (Minneapolis) MN Register Description
Nov 11-12 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Nov 11-12 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
Nov 13-15 Designing with VHDL (LANG-VHDL) Orono (Minneapolis) MN Register Description
Nov 14-15 Designing with SystemVerilog (LANG-SVDES) Orono (Minneapolis) MN Register Description
Nov 18-19 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Naperville IL Full Description
Nov 21-22 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Nov 21-22 Embedded Design with PetaLinux Tools (EMBD-PLNX) Schaumburg IL Register Description
Nov 25-27 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Orono (Minneapolis) MN Register Description
Nov 25-27 Designing with Verilog (LANG-VERILOG) Orono (Minneapolis) MN Register Description
December 2019
Dec 2-4 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Orono (Minneapolis) MN Register Description
Dec 2-3 Verification with SystemVerilog (LANG-SVVER) Orono (Minneapolis) MN Register Description
Dec 5-6 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Dec 5-6 Advanced SDSoC Development Environment and Methodology (EMBD-ADVSDSOC) Orono (Minneapolis) MN Register Description
Dec 9-10 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Dec 9-11 Designing with VHDL (LANG-VHDL) Orono (Minneapolis) MN Register Description
Dec 12-13 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs (EMBD-OCLSDA) Schaumburg IL Register Description
Dec 12-12 Advanced Features and Techniques of Embedded Systems Software Design (EMBD-ADVSW) Orono (Minneapolis) MN Register Description
Dec 16-16 Advanced Features and Techniques of Embedded Systems Software Design (EMBD-ADVSW) Overland Park KS Register Description
Dec 17-18 Embedded Design with PetaLinux Tools (EMBD-PLNX) Overland Park KS Register Description
Dec 19-20 Verification with SystemVerilog (LANG-SVVER) Orono (Minneapolis) MN Register Description
Dec 26-27 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Dec 26-27 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Orono (Minneapolis) MN Register Description

Student Cancellation Policy

  • Students cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
  • Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
  • Student cancellations must be sent here.

Course Cancellation Policy

  • We regret from time to time classes will need to be rescheduled or cancelled.
  • In the event of cancellation, live on-line training may be offered as a substitute.
  • Morgan Advanced Programmable Systems, Inc. may cancel a class up to 7 days before the scheduled start date of the class; all students will be entitled to a 100% refund.
  • Under no circumstances is Morgan Advanced Programmable Systems, Inc. responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.
  • For additional information or to schedule a private class contact us here.