November 2019
Nov 21-22 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Nov 25-27 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Orono (Minneapolis) MN Register Description
Nov 25-26 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Schaumburg IL Register Description
December 2019
Dec 5-6 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Dec 5-6 Advanced SDSoC Development Environment and Methodology (EMBD-ADVSDSOC) Orono (Minneapolis) MN Register Description
Dec 9-10 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Dec 9-11 Designing with VHDL (LANG-VHDL) Orono (Minneapolis) MN Register Description
Dec 11-13 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Schaumburg IL Register Description
Dec 12-13 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs (EMBD-OCLSDA) Schaumburg IL Register Description
Dec 12-12 Advanced Features and Techniques of Embedded Systems Software Design (EMBD-ADVSW) Orono (Minneapolis) MN Register Description
Dec 16-17 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Schaumburg IL Register Description
Dec 18-20 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Schaumburg IL Register Description
Dec 19-20 Verification with SystemVerilog (LANG-SVVER) Orono (Minneapolis) MN Register Description
Dec 26-27 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Dec 26-27 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Orono (Minneapolis) MN Register Description
January 2020
Jan 2-3 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
Jan 2-3 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Jan 6-8 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Orono (Minneapolis) MN Register Description
Jan 6-8 Designing with Verilog (LANG-VERILOG) Orono (Minneapolis) MN Register Description
Jan 9-10 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Jan 9-10 Embedded Design with PetaLinux Tools (EMBD-PLNX) Orono (Minneapolis) MN Register Description
Jan 13-15 Designing with VHDL (LANG-VHDL) Orono (Minneapolis) MN Register Description
Jan 13-15 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Orono (Minneapolis) MN Register Description
Jan 15-17 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Orono (Minneapolis) MN Register Description
Jan 16-17 DSP Design Using System Generator (DSP-SYSGEN) Orono (Minneapolis) MN Register Description
Jan 20-21 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs (EMBD-OCLSDA) Schaumburg IL Register Description
Jan 20-22 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Schaumburg IL Register Description
Jan 23-24 Embedded Systems Software Design (EMBD-SW) Schaumburg IL Register Description
Jan 23-24 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Schaumburg IL Register Description
Jan 27-28 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs (EMBD-OCLSDA) Orono (Minneapolis) MN Register Description
Jan 27-28 Designing with SystemVerilog (LANG-SVDES) Orono (Minneapolis) MN Register Description
Jan 30-31 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Orono (Minneapolis) MN Register Description
Jan 30-30 Essential Tcl Scripting for the Vivado Design Suite (LANG-TCL) Orono (Minneapolis) MN Register Description
February 2020
Feb 3-4 Verification with SystemVerilog (LANG-SVVER) Orono (Minneapolis) MN Register Description
Feb 3-4 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Feb 3-4 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
Feb 5-7 Designing with VHDL (LANG-VHDL) Orono (Minneapolis) MN Register Description
Feb 5-7 Zynq Master Training for Experienced FPGA Engineers (EMBD-33040) Orono (Minneapolis) MN Register Description
Feb 6-7 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Orono (Minneapolis) MN Register Description
Feb 10-12 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Orono (Minneapolis) MN Register Description
Feb 10-11 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Orono (Minneapolis) MN Register Description
Feb 12-14 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) Orono (Minneapolis) MN Register Description
Feb 13-14 DSP Design Using System Generator (DSP-SYSGEN) Orono (Minneapolis) MN Register Description
Feb 13-14 Advanced VHDL (LANG-ADVVHDL) Orono (Minneapolis) MN Register Description
Feb 17-19 Designing with Verilog (LANG-VERILOG) Orono (Minneapolis) MN Register Description
Feb 17-18 C-based Design: High-Level Synthesis with the Vivado HLx Tool (DSP-HLS) Schaumburg IL Register Description
Feb 17-18 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Orono (Minneapolis) MN Register Description
Feb 20-21 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Feb 20-21 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs (EMBD-OCLSDA) Orono (Minneapolis) MN Register Description
Feb 20-21 Designing with SystemVerilog (LANG-SVDES) Orono (Minneapolis) MN Register Description
Feb 24-25 Embedded Design with PetaLinux Tools (EMBD-PLNX) Orono (Minneapolis) MN Register Description
Feb 24-25 Zynq UltraScale+ MPSoC for the Software Developer (EMBD-ZUPSW) Orono (Minneapolis) MN Register Description
Feb 24-26 Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) Schaumburg IL Register Description
Feb 27-27 Zynq UltraScale+ MPSoC for the Hardware Designer (EMBD-ZUPHW) Orono (Minneapolis) MN Register Description
Feb 27-27 Essential Tcl Scripting for the Vivado Design Suite (LANG-TCL) Orono (Minneapolis) MN Register Description
Feb 27-28 Verification with SystemVerilog (LANG-SVVER) Orono (Minneapolis) MN Register Description

Student Cancellation Policy

  • Students cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
  • Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
  • Student cancellations must be sent here.

Course Cancellation Policy

  • We regret from time to time classes will need to be rescheduled or cancelled.
  • In the event of cancellation, live on-line training may be offered as a substitute.
  • Morgan Advanced Programmable Systems, Inc. may cancel a class up to 7 days before the scheduled start date of the class; all students will be entitled to a 100% refund.
  • Under no circumstances is Morgan Advanced Programmable Systems, Inc. responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.
  • For additional information or to schedule a private class contact us here.