Hardware Descriptor languages (HDLs) have been the way of doing design entry for FPGAs and ASICs for 20+ years. In the hands of an experienced engineer, designs that are reusable, scalable, testable, and maintainable are easy to achieve. However, engineers who are recent graduates often need additional training beyond the academic training they received at the University.
As FPGAs today have more resources, other design methodologies are gaining in popularity. HLS based tools allow algorithm designers to work in the C/C++ world, and in conjunction with directives, allow trade offs to be made between latency and real estate.
Other design entry methods exist for systems engineer familiar with Matlab's SimuLink tool. SystemGenerator allows the system engineer to rapidly prototype and test signal processing algorithms using the familiar simulink interface. Furthermore, the system engineer can speed up their design verification by utilizing SystemGenerator's Hardware In the Loop (HWIL) feature, allowing cycle by cycle and bit for bit comparisons of SystemGenerator models with an implemented design.
Tcl is a powerful scripting language that allows engineers to automate synthesis, implementation, verification, and even HWIL verification of FPGAs. For example, nightly regressing tests can be written to discover design defects earlier in the design cycle.
Whether you're interested in learning an HDL, HLS, SystemGenerator, or Vitis, the following training is of great value to get the most performance out of the available FPGA/SoC/ACAP resources.
- C-based HLS Coding for Hardware Designers (Legacy Vivado 2012.2)
- C-based HLS Coding for Software Designers (Legacy Vivado 2012.2)
- C-based Design High-Level Synthesis with the Vivado HLx Tool
Verilog and SystemVerilog
C / C ++
- C Language Programming with SDK (Legacy Vivado 2014.1)
- Embedded C-C++ SDSoC Development Environment and Methodology
- Embedded Systems Software Design
- Embedded Design with PetaLinux Tools
- SDSoC Development Environment and Methodology
XDC (Xilinx Design Constraints and Timing Analysis)