A wide variety of courses on FPGA, MPSoC, and ACAP design
The following course descriptions with pricing. If a class you need is not on the schedule, please feel free to contact us. Please note that extra fees may apply to update some but not all legacy courses. Please contact us for details. Legacy courses are indicated with (Legacy Tool Version) below.
Most active
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- AI-ACCEL: Accelerating Applications with the Vitis Unified Software Environment (2019.2)
- CONN-PCIE: Designing an Integrated PCI Express System (2018.3)
- CONN-RFSOC: Designing with the Zynq UltraScale+ RFSoC (2019.1)
- DSP-HLS: C-based Design: High-Level Synthesis with the Vivado HLx Tool (2019.1)
- DSP-SYSGEN: DSP Design Using System Generator (2019.2)
- EMBD-33040: Zynq Master Training for Experienced FPGA Engineers (2019.2)
- EMBD-ADVSW: Advanced Features and Techniques of Embedded Systems Software Design (2017.3)
- EMBD-HW: Embedded Systems Design (2019.1)
- EMBD-PLNX: Embedded Design with PetaLinux Tools (2019.1)
- EMBD-SW: Embedded Systems Software Design (2019.2)
- EMBD-VITIS: Migrating to the Vitis Embedded Software Development IDE Workshop (2019.2)
- EMBD-uPS: Essentials of Microprocessors (All)
- EMBD-ZSA: Zynq All Programmable SoC System Architecture (2018.1)
- EMBD-ZUPHW: Zynq UltraScale+ MPSoC for the Hardware Designer (2019.1)
- EMBD-ZUPSA: Zynq UltraScale+ MPSoC for the System Architect (2019.1)
- EMBD-ZUPSW: Zynq UltraScale+ MPSoC for the Software Developer (2019.1)
- FPGA-7SERIES: Designing with the 7 Series Families
- FPGA-PR: Xilinx Partial Reconfiguration Tools and Techniques (2019.1)
- FPGA-USM: UltraScale Architecture Design Migration Workshop (2019.1)
- FPGA-US1D: UltraScale and UltraScale+ Architectures Workshop (2019.1)
- FPGA-V4ISE: Vivado Design Suite for ISE PN Users (2018.1)
- FPGA-VDES1: Designing FPGAs Using the Vivado Design Suite 1 (2019.2)
- FPGA-VDES2: Designing FPGAs Using the Vivado Design Suite 2 (2019.2)
- FPGA-VDES3: Designing FPGAs Using the Vivado Design Suite 3 (2019.2)
- FPGA-VDES4: Designing FPGAs Using the Vivado Design Suite 4 (2019.2)
- FPGA-US: Designing with the UltraScale and UltraScale+ Architectures (2019.1)
- FPGA-VAXDC4ISE: Vivado Design Suite Advanced XDC and STA (2019.1)
- FPGA-VDM: UltraFast Design Methodology (2019.1)
- FPGA-STAXDCADV: Vivado STA XDC and Advanced Tools and Techniques of Vivado Design Suite (2019.2)
- LANG-ADVVHDL: Advanced VHDL
- LANG-SVDES: Designing with SystemVerilog (2019.1)
- LANG-SVVER: Verification with SystemVerilog (2019.1)
- LANG-TCL: Essential Tcl Scripting for the Vivado Design Suite (All)
- LANG-VERILOG: Designing with Verilog (2019.1)
- LANG-VHDL: Designing with VHDL
Legacy
- CSP-22000: Debugging Techniques Using the ChipScope Pro Tools (ISE 14.2)
- CONN-13000: How to Design a Xilinx Connectivity System in 1 Day (2013.2)
- CONN-EMAC: Designing with Ethernet MAC Controllers (2014.3)
- CONN-MGTUS: Designing with UltraScale FPGA Transceivers (2015.3)
- CONN-MGT: Designing with Multi-Gigabit Serial IO (2015.1)
- CONN-MIF: How to Design a High-Speed Memory Interface (2015.1)
- CONN-PCIE-PROT: PCIe Protocol Overview
- CONN-SI: Signal Integrity and Board Design for Xilinx FPGAs (2012.4)
- CONN-TRX: Designing with Xilinx Serial Transceivers (2016.3)
- DSP-13000: How to Design a Xilinx Digital Signal Processing System in 1 Day (ISE 13.1)
- DSP-22000: C-based HLS Coding for Hardware Designers (2012.2)
- DSP-23000: C-based HLS Coding for Software Designers (2012.2)
- DSP-ESS: Essential DSP Implementation Techniques for Xilinx FPGAs (All, but please call)
- EMBD-12000: C Language Programming with SDK (2014.1)
- EMBD-ADVHW: Advanced Features and Techniques of Embedded Systems Design (2017.3)
- EMBD-ADVSDSOC: Advanced SDSoC Development Environment and Methodology (2017.4)
- EMBD-AWS: Developing AWS F1 Applications Using the SDAccel Environment (2017.4)
- EMBD-OCLSDA: Developing and Optimizing Applications Using the OpenCL Framework for FPGAs (2018.3)
- EMBD-SDSOC: SDSoC Development Environment and Methodology (2018.3)
- EMBD-SZS01: Zynq Smarter Solutions Decision Maker 1 Day Seminar (2015.1)
- EMBD-SZS01: Zynq Smarter Solutions Decision Maker half-day Seminar (2015.1)
- FPGA-22000: Advanced Design with the PlanAhead Analysis and Design Tool (ISE 14.7)
- FPGA-24000: FPGA Power Optimization (2014.3)
- FPGA-33000: Advanced FPGA Implementation (ISE 14.7)
- FPGA-VATT: Advanced Tools and Techniques of the Vivado Design Suite (2015.3)
- FPGA-VDF: Vivado Design Suite Tool Flow (2015.3)
- FPGA-VSTAXDC: Vivado Design Suite Static Timing Analysis and Xilinx Design Constraints (2015.3)
- FPGA-VLA: Debugging Techniques Using the Vivado Logic Analyzer (2015.3)
- INTRO-ZARCH: Introduction to the Zynq SoC Architecture (2018.1)
- ISM-11000: Industrial Motor Control Using FPGAs and SoCs (ISE 14.2)
- MILAE10000: TMRTool (ISE 7.1)
- S6V6-21000: Designing with the Spartan-6 and Virtex-6 Families (ISE 13.1)
- S6-21000: Designing with the Spartan-6 Family (ISE 13.1)
- VIVA-12000: Vivado Design Suite Hands-on Introductory Workshop (2014.1)