A wide variety of courses on FPGA, MPSoC, and ACAP design
The following course descriptions with pricing. If a class you need is not on the schedule, please feel free to contact us. Please note that extra fees may apply to update some but not all legacy courses. Please contact us for details. Legacy courses are indicated with (Legacy Tool Version) below.
- ACAP-AIE1: Designing with Versal AI Engine 1
- ACAP-AIE2: Designing with Versal AI Engine 2
- ACAP-AIE3: Designing with Versal AI Engine 3
- ACAP-ARCH: Designing with the Versal ACAP Architecture and Methodology
- ACAP-NOC: Designing with the Versal ACAP Network on Chip
- AI-ACCEL: Accelerating Applications with the Vitis Unified Software Environment
- AI-INFER: Developing AI Inference Solutions with the Vitis AI Platform
- CONN-PCIE: Designing an Integrated PCI Express System
- CONN-PCIE-PROT: PCIe Protocol Overview
- CONN-RFSOC: Designing with the Zynq UltraScale+ RFSoC
- CONN-SI: Signal Integrity and Board Design for Xilinx FPGAs
- CONN-TRX: Designing with Xilinx Serial Transceivers
- DSP-HLS: C-based Design: High-Level Synthesis with the Vivado HLx Tool
- DSP-SYSGEN: DSP Design Using System Generator
- EMBD-33040: Zynq Master Training for Experienced FPGA Engineers
- EMBD-88080: Xilinx Embedded Design for Rapid Development
- EMBD-AIEDGE: Developing Xilinx AI Solutions for Edge-based Applications
- EMBD-HW: Embedded Systems Design
- EMBD-MMEDIA: Developing Multimedia Solutions with the VCU and GStreamer
- EMBD-PLNX: Embedded Design with PetaLinux Tools
- EMBD-SW: Embedded Systems Software Design
- EMBD-uPS: Essentials of Microprocessors
- EMBD-VITIS: Migrating to the Vitis Embedded Software Development IDE Workshop
- EMBD-VITIS2: Migrating to the Vitis Embedded Software Development IDE 2-day Workshop
- EMBD-ZSA: Zynq All Programmable SoC System Architecture
- EMBD-ZUPHW: Zynq UltraScale+ MPSoC for the Hardware Designer
- EMBD-ZUPSA: Zynq UltraScale+ MPSoC for the System Architect
- EMBD-ZUPSW: Zynq UltraScale+ MPSoC for the Software Developer
- FPGA-7SERIES: Designing with the 7 Series Families
- FPGA-AICLOUD: Developing Xilinx AI Solutions for Cloud-based Applications
- FPGA-ALVEO: Using Xilinx Alveo Cards to Accelerate Dynamic Workloads
- FPGA-PR: Xilinx Partial Reconfiguration Tools and Techniques
- FPGA-US1D: UltraScale and UltraScale+ Architectures Workshop
- FPGA-STAXDCADV: Vivado STA XDC and Advanced Tools and Techniques of Vivado Design Suite
- FPGA-VAXDC4ISE: Vivado Design Suite Advanced XDC and STA
- FPGA-VDES1: Designing FPGAs Using the Vivado Design Suite 1
- FPGA-VDES2: Designing FPGAs Using the Vivado Design Suite 2
- FPGA-VDES3: Designing FPGAs Using the Vivado Design Suite 3
- FPGA-VDES4: Designing FPGAs Using the Vivado Design Suite 4
- FPGA-VDM: UltraFast Design Methodology
- INTRO-ZARCH: Introduction to the Zynq SoC Architecture
- LANG-ADVVHDL: Advanced VHDL
- LANG-SVDES: Designing with SystemVerilog
- LANG-SVVER: Verification with SystemVerilog
- LANG-VERILOG: Designing with Verilog
- LANG-VHDL: Designing with VHDL