With Xilinx's selection of 7-series Zynq SoCs, Ultrascale+ MPSoCs, and Versal ACAPs, the ability to integrate custom intellectual property through the IP integrator is phenomenal. However, training is essential to creating easy to test, easy to implement, and easy to verify designs. Below, you'll find course descriptions for Embedded Design for architects, software, and hardware engineers.
AI, ML,
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- AI-ACCEL: Accelerating Applications with the Vitis Unified Software Environment
- FPGA-AICLOUD: Developing Xilinx AI Solutions for Cloud-based Applications
- EMBD-AIEDGE: Developing Xilinx AI Solutions for Edge-based Applications
- AI-INFER: Developing AI Inference Solutions with the Vitis AI Platform
- ACAP-AIE1: Designing with Versal AI Engine 1
- ACAP-AIE2: Designing with Versal AI Engine 2
- ACAP-AIE3: Designing with Versal AI Engine 3
- ACAP-ARCH: Designing with the Versal ACAP Architecture and Methodology
Covers both IP Integrator and Vitis SDK, but with emphasis on IPI
Covers both IP Integrator and Vitis SDK, with emphasis on Vitis
Zynq MPSoC and RFSoC
Zynq 7000
HLS
Xilinx PetaLinux Tools
Touches on integrating SysGen designs into IPI