Note: Courses can be run at your site, or at Morgan Advanced Programmable Systems, at Orono, MN, or at a conference room near you--for those companies that are allowing visitors. Please contact us at (952) 486-8881 or via this contact form.
Start | Days | Course | City | State | Register |
---|---|---|---|---|---|
11/05/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Online | Online | Closed |
11/05/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Hoffman Estates | IL | Closed |
11/06/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Saint Louis | MO | Full |
11/07/2024 | 2 | Designing with Versal AI Engine 2 Graph Programming with AI Engine Kernels (ACAP-AIE2) | Fargo | ND | Closed |
11/07/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Orono (Minneapolis) | MN | Closed |
11/07/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Closed |
11/11/2024 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Orono (Minneapolis) | MN | Full |
11/11/2024 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Online | Online | Full |
11/12/2024 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Orono (Minneapolis) | MN | Closed |
11/12/2024 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Online | Online | Closed |
11/13/2024 | 1 | Introduction to AMD Versal Adaptive SoC (ASOC-INTRO) | Online | Online | Register |
11/13/2024 | 2 | DSP Design Using System Generator (DSP-SYSGEN) | Orono (Minneapolis) | MN | Closed |
11/13/2024 | 2 | DSP Design Using System Generator (DSP-SYSGEN) | Online | Online | Closed |
11/13/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Orono (Minneapolis) | MN | Full |
11/13/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Full |
11/14/2024 | 2 | Designing with Versal AI Engine 3 Kernel Programming and Optimization (ACAP-AIE3) | Olathe | KS | Closed |
11/18/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Orono (Minneapolis) | MN | Full |
11/18/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Online | Online | Full |
11/18/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Schaumburg | IL | Closed |
11/18/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Online | Online | Closed |
11/18/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Orono (Minneapolis) | MN | Closed |
11/18/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) | Online | Online | Closed |
11/19/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Orono (Minneapolis) | MN | Full |
11/19/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Online | Online | Full |
11/19/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Orono (Minneapolis) | MN | Closed |
11/19/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) | Online | Online | Closed |
11/25/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Orono (Minneapolis) | MN | Full |
11/25/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Online | Online | Full |
12/02/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Schaumburg | IL | Closed |
12/02/2024 | 1 | Introduction to the Zynq SoC Architecture (INTRO-ZARCH) | Online | Online | Closed |
12/03/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Orono (Minneapolis) | MN | Full |
12/03/2024 | 4 | Xilinx Rapid Development Embedded Design (EMBD-88080) | Online | Online | Full |
12/05/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Schaumburg | IL | Closed |
12/09/2024 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Schaumburg | IL | Closed |
12/09/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Orono (Minneapolis) | MN | Full |
12/09/2024 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Online | Online | Full |
12/09/2024 | 3 | Designing with VHDL (LANG-VHDL) | Online | Online | Closed |
12/12/2024 | 2 | Advanced VHDL (LANG-ADVVHDL) | Online | Online | Closed |
12/13/2024 | 1 | Designing with the Versal ACAP: Network on Chip (ACAP-NOC) | Schaumburg | IL | Full |
12/16/2024 | 2 | Designing with Versal AI Engine 1 Architecture and Design Flow (ACAP-AIE1) | Schaumburg | IL | Register |
12/16/2024 | 3 | Designing with Verilog (LANG-VERILOG) | Orono (Minneapolis) | MN | Register |
12/16/2024 | 3 | Designing with Verilog (LANG-VERILOG) | Online | Online | Register |
12/19/2024 | 2 | Designing with Versal AI Engine 2 Graph Programming with AI Engine Kernels (ACAP-AIE2) | Schaumburg | IL | Register |
12/19/2024 | 2 | Designing with SystemVerilog (LANG-SVDES) | Orono (Minneapolis) | MN | Register |
12/19/2024 | 2 | Designing with SystemVerilog (LANG-SVDES) | Online | Online | Register |
12/23/2024 | 2 | Verification with SystemVerilog (LANG-SVVER) | Orono (Minneapolis) | MN | Register |
12/23/2024 | 2 | Verification with SystemVerilog (LANG-SVVER) | Online | Online | Register |
12/30/2024 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Orono (Minneapolis) | MN | Register |
12/30/2024 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Online | Online | Register |
01/02/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) | Schaumburg | IL | Register |
01/03/2025 | 1 | Essentials of Microprocessors (EMBD-uPS) | Overland Park | KS | Register |
01/06/2025 | 2 | Embedded Systems Software Design (EMBD-SW) | Overland Park | KS | Register |
01/06/2025 | 2 | Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) | Schaumburg | IL | Register |
01/08/2025 | 3 | STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite (FPGA-STAXDCADV) | Schaumburg | IL | Register |
01/13/2025 | 3 | Designing with the Zynq UltraScale+ RFSoC (CONN-RFSOC) | Schaumburg | IL | Register |
01/16/2025 | 2 | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite (FPGA-DFX) | Schaumburg | IL | Register |
01/21/2025 | 2 | Designing with the IP Integrator Tool (FPGA-IPI) | Overland Park | KS | Register |
Don't see a class?
If you do not see a class that you're interested in on the schedule, please either give us a call or contact us. We will work to rearrange the schedule so that key members of your team can get the Xilinx training they need as soon as possible.
Cancellation Policies
These are our cancellation policies:
Student Cancellation Policy
- Students cancellations received more than 7 days before the first day of class are entitled to a 100% refund. Refunds will be processed within 14 days.
- Student cancellations received less than 7 days before the first day of class are entitled to a 100% credit toward a future class.
- Student cancellations must be sent here.
Course Cancellation Policy
- We regret that from time to time classes will need to be rescheduled or cancelled.
- In the event of cancellation, live on-line training may be offered as a substitute.
- Morgan Advanced Programmable Systems, Inc. may cancel a class up to 7 days before the scheduled start date of the class; all students will be entitled to a 100% refund.
- Under no circumstances is Morgan Advanced Programmable Systems, Inc. responsible or liable for travel, lodging or other incidental costs. Please be aware of this cancellation policy when making your arrangements.
- For additional information or to schedule a private class contact us here.