Xilinx Design Constraints (XDC) and Static Timing Analysis (STA) are two critical components that will make or break your design schedule. These courses will help ensure that your product works as well in the field as it does in simulation and in the lab.
- FPGA-VDM: UltraFast Design Methodology
- FPGA-STAXDCADV: Vivado STA XDC and Advanced Tools and Techniques of Vivado Design Suite
- FPGA-DSGNCLOSURE: Design Closure Techniques
- FPGA-VDES1: Designing FPGAs Using the Vivado Design Suite 1
- FPGA-VDES2: Designing FPGAs Using the Vivado Design Suite 2
- FPGA-VDES3: Designing FPGAs Using the Vivado Design Suite 3
- FPGA-VDES4: Designing FPGAs Using the Vivado Design Suite 4