With Xilinx's selection of Versal, Ultrascale+ MPSoC/RFSoCs, and 7-series Zynq SoCs, the ability to integrate custom intellectual property through the IP integrator is phenomenal. However, training is essential to creating easy to test, easy to implement, and easy to verify designs. Below, you'll find course descriptions for Embedded Design for architects, software, and hardware engineers.
- EMBD-ZUPHW: Zynq UltraScale+ MPSoC for the Hardware Designer
- EMBD-ZUPSA: Zynq UltraScale+ MPSoC for the System Architect
- EMBD-ZUPSW: Zynq UltraScale+ MPSoC for the Software Developer
- EMBD-88080: Xilinx Embedded Design for Rapid Development
- EMBD-PLNX: Embedded Design with PetaLinux Tools
- EMBD-HW: Embedded Systems Design
- EMBD-SW: Embedded Systems Software Design
- EMBD-VITIS: Migrating to the Vitis Embedded Software Development IDE Workshop
- EMBD-HET: Embedded Heterogeneous Design
- AI-INFER: Developing AI Inference Solutions with the Vitis AI Platform
- AIE-ARCH: Designing with Versal AI Engine: Architecture and Design Flow - 1
- AIE-GRAPH: Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
- AIE-KERNEL: Designing with Versal AI Engine: Kernel Programming and Optimization - 3
- AIE-DSP: Designing with Versal AI Engine: DSP Applications
- CONN-RFSOC: Designing with the Zynq UltraScale+ RFSoC
- ACAP-DEBUG: Designing with the Versal Adaptive SoC Hardware Debug
- ACAP-MEM: Designing with the Versal Adaptive SoC Memory Interfaces
- ACAP-MGRT: Migrating from UltraScale+ Devices to Versal Adaptive SoCs
- ACAP-NOC: Designing with the Versal Adaptive SoC Network on Chip
- ACAP-PCIE: Designing with the Versal Adaptive SoC PCI Express Systems
- ACAP-POWER-BD: Designing with the Versal Adaptive SoC Power and Board Design
- ACAP-QSTART: Designing with the Versal Adaptive SoC Quick Start
- ACAP-TRX: Designing with the Versal Adaptive SoC Serial Transceivers
- ACAP-VARCH: Designing with the Versal Adaptive SoC Architecture
- ACAP-VDM: Designing with the Versal Adaptive SoC Design Methodology