As FPGAs and Adaptive SoC (formerly ACAPs) devices break the 50 billion transistor threshold, traditional design techniques using HDLs and baremetal operating systems are not scaling in a way that allows a reasonable time to market with a reasonably sized design team. Engineers today are expected to do more in less time and more reliably. Fortunately, AMD (Formerly Xilinx) understands this situation and has invested in new design entry methodologies that will scale to state of the art FPGAs. Vitis is an exciting new unified software development platform to do much more in less time with fewer engineers.
Vitis
- EMBD-VITIS: Migrating to the Vitis Embedded Software Development IDE Workshop
- AI-ACCEL: Accelerating Applications with the Vitis Unified Software Environment
HLS
AI (HLS and embedded recommended prerequisites)
AI Engines
- AIE-QSTART: Designing with Versal AI Engine Quick Start
- AIE-ARCH: Designing with Versal AI Engine Architecture and Design Flow - 1
- AIE-GRAPH: Designing with Versal AI Engine Graph Programming with AI Engine Kernels - 2
- AIE-KERNEL: Designing with Versal AI Engine Kernel Programming and Optimization - 3
- AIE-DSP: Designing with Versal AI Engine DSP Applications